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https://github.com/sampletext32/ParkanPlayground.git
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Updated instruction handlers to use Type and StructuredOperands instead of Mnemonic and Operands
This commit is contained in:
bird_egop
@ -1,3 +1,5 @@
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using X86Disassembler.X86.Operands;
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// <summary>
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@ -5,66 +7,64 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// </summary>
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public class LoadStoreInt16Handler : InstructionHandler
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{
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// Memory operand mnemonics for DF opcode - load/store int16, misc
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private static readonly string[] MemoryMnemonics =
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// Memory operand instruction types for DF opcode - load/store int16, misc
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private static readonly InstructionType[] MemoryInstructionTypes =
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[
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"fild", // 0 - 16-bit integer
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"??", // 1
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"fist", // 2 - 16-bit integer
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"fistp", // 3 - 16-bit integer
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"fbld", // 4 - 80-bit packed BCD
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"fild", // 5 - 64-bit integer
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"fbstp", // 6 - 80-bit packed BCD
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"fistp" // 7 - 64-bit integer
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InstructionType.Unknown, // fild - not in enum
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InstructionType.Unknown, // ??
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InstructionType.Unknown, // fist - not in enum
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InstructionType.Unknown, // fistp - not in enum
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InstructionType.Unknown, // fbld - not in enum
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InstructionType.Unknown, // fild - 64-bit integer - not in enum
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InstructionType.Unknown, // fbstp - not in enum
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InstructionType.Unknown // fistp - 64-bit integer - not in enum
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex OperandIndex, FpuRegisterIndex? SrcIndex)> RegisterOperations = new()
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{
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// FFREEP ST(i)
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{ (RegisterIndex.A, RegisterIndex.A), ("ffreep", "st(0)") },
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{ (RegisterIndex.A, RegisterIndex.C), ("ffreep", "st(1)") },
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{ (RegisterIndex.A, RegisterIndex.D), ("ffreep", "st(2)") },
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{ (RegisterIndex.A, RegisterIndex.B), ("ffreep", "st(3)") },
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{ (RegisterIndex.A, RegisterIndex.Sp), ("ffreep", "st(4)") },
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{ (RegisterIndex.A, RegisterIndex.Bp), ("ffreep", "st(5)") },
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{ (RegisterIndex.A, RegisterIndex.Si), ("ffreep", "st(6)") },
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{ (RegisterIndex.A, RegisterIndex.Di), ("ffreep", "st(7)") },
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{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, null) },
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{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST1, null) },
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{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST2, null) },
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{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST3, null) },
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{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST4, null) },
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{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST5, null) },
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{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST6, null) },
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{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST7, null) },
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// Special cases
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{ (RegisterIndex.B, RegisterIndex.A), ("fxch", "") },
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{ (RegisterIndex.C, RegisterIndex.A), ("fstp", "st(1)") },
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{ (RegisterIndex.D, RegisterIndex.A), ("fstp", "st(1)") },
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{ (RegisterIndex.B, RegisterIndex.A), (InstructionType.Fxch, FpuRegisterIndex.ST0, null) },
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{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Fstp, FpuRegisterIndex.ST1, null) },
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{ (RegisterIndex.D, RegisterIndex.A), (InstructionType.Fstp, FpuRegisterIndex.ST1, null) },
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// FUCOMIP ST(0), ST(i)
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{ (RegisterIndex.Di, RegisterIndex.A), ("fucomip", "st(0), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.C), ("fucomip", "st(0), st(1)") },
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{ (RegisterIndex.Di, RegisterIndex.D), ("fucomip", "st(0), st(2)") },
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{ (RegisterIndex.Di, RegisterIndex.B), ("fucomip", "st(0), st(3)") },
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{ (RegisterIndex.Di, RegisterIndex.Sp), ("fucomip", "st(0), st(4)") },
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{ (RegisterIndex.Di, RegisterIndex.Bp), ("fucomip", "st(0), st(5)") },
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{ (RegisterIndex.Di, RegisterIndex.Si), ("fucomip", "st(0), st(6)") },
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{ (RegisterIndex.Di, RegisterIndex.Di), ("fucomip", "st(0), st(7)") },
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{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
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// FCOMIP ST(0), ST(i)
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{ (RegisterIndex.Sp, RegisterIndex.A), ("fcomip", "st(0), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.C), ("fcomip", "st(0), st(1)") },
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{ (RegisterIndex.Sp, RegisterIndex.D), ("fcomip", "st(0), st(2)") },
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{ (RegisterIndex.Sp, RegisterIndex.B), ("fcomip", "st(0), st(3)") },
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{ (RegisterIndex.Sp, RegisterIndex.Sp), ("fcomip", "st(0), st(4)") },
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{ (RegisterIndex.Sp, RegisterIndex.Bp), ("fcomip", "st(0), st(5)") },
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{ (RegisterIndex.Sp, RegisterIndex.Si), ("fcomip", "st(0), st(6)") },
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{ (RegisterIndex.Sp, RegisterIndex.Di), ("fcomip", "st(0), st(7)") }
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{ (RegisterIndex.Sp, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.Sp, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.Sp, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.Sp, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.Sp, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.Sp, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.Sp, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.Sp, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) }
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};
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/// <summary>
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/// Initializes a new instance of the LoadStoreInt16Handler class
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/// </summary>
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/// <param name="codeBuffer">The buffer containing the code to decode</param>
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/// <param name="decoder">The instruction decoder that owns this handler</param>
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/// <param name="length">The length of the buffer</param>
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public LoadStoreInt16Handler(byte[] codeBuffer, InstructionDecoder decoder, int length)
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: base(codeBuffer, decoder, length)
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public LoadStoreInt16Handler(InstructionDecoder decoder)
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: base(decoder)
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{
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}
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@ -92,7 +92,7 @@ public class LoadStoreInt16Handler : InstructionHandler
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}
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// Read the ModR/M byte
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var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
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var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
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// Check for FNSTSW AX (DF E0)
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if (mod == 3 && reg == RegisterIndex.Bp && rm == RegisterIndex.A)
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@ -104,43 +104,65 @@ public class LoadStoreInt16Handler : InstructionHandler
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// Handle based on addressing mode
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if (mod != 3) // Memory operand
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{
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// Set the mnemonic based on the reg field
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instruction.Mnemonic = MemoryMnemonics[(int)reg];
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// Set the instruction type based on the reg field
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instruction.Type = MemoryInstructionTypes[(int)reg];
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// Get the base operand without size prefix
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string baseOperand = memOperand.Replace("dword ptr ", "");
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// Apply the appropriate size prefix based on the operation
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// Set the size based on the operation
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // 16-bit integer operations
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{
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instruction.Operands = $"word ptr {baseOperand}";
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// Set to 16-bit for integer operations
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memoryOperand.Size = 16;
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}
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else if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // 64-bit integer operations
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{
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instruction.Operands = $"qword ptr {baseOperand}";
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// Set to 64-bit for integer operations
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memoryOperand.Size = 64;
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}
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else if (reg == RegisterIndex.Si || reg == RegisterIndex.Sp) // 80-bit packed BCD operations
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{
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instruction.Operands = $"tbyte ptr {baseOperand}";
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}
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else // Other operations
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{
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instruction.Operands = memOperand;
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// Set to 80-bit for BCD operations
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memoryOperand.Size = 80;
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}
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// Set the structured operands
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instruction.StructuredOperands =
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[
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memoryOperand
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];
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}
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else // Register operand (ST(i))
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{
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// Look up the register operation in our dictionary
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// Look up the instruction type in the register operations dictionary
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if (RegisterOperations.TryGetValue((reg, rm), out var operation))
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{
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instruction.Mnemonic = operation.Mnemonic;
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instruction.Operands = operation.Operands;
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instruction.Type = operation.Type;
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// Create the FPU register operands
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var destOperand = OperandFactory.CreateFPURegisterOperand(operation.OperandIndex);
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// Set the structured operands
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if (operation.SrcIndex.HasValue)
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{
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var srcOperand = OperandFactory.CreateFPURegisterOperand(operation.SrcIndex.Value);
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instruction.StructuredOperands =
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[
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destOperand,
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srcOperand
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];
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}
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else
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{
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instruction.StructuredOperands =
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[
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destOperand
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];
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}
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}
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else
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{
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// Unknown instruction
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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instruction.Type = InstructionType.Unknown;
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instruction.StructuredOperands = [];
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}
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}
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