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https://github.com/sampletext32/ParkanPlayground.git
synced 2025-06-20 08:18:36 +03:00
Updated instruction handlers to use Type and StructuredOperands instead of Mnemonic and Operands
This commit is contained in:
bird_egop
@ -1,3 +1,5 @@
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using X86Disassembler.X86.Operands;
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// <summary>
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@ -5,95 +7,93 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// </summary>
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public class LoadStoreInt32Handler : InstructionHandler
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{
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// Memory operand mnemonics for DB opcode - load/store int32, misc
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private static readonly string[] MemoryMnemonics =
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// Memory operand instruction types for DB opcode - load/store int32, misc
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private static readonly InstructionType[] MemoryInstructionTypes =
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[
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"fild", // 0 - 32-bit integer
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"??", // 1
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"fist", // 2 - 32-bit integer
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"fistp", // 3 - 32-bit integer
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"??", // 4
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"fld", // 5 - 80-bit extended precision
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"??", // 6
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"fstp" // 7 - 80-bit extended precision
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InstructionType.Unknown, // fild - not in enum
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InstructionType.Unknown, // ??
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InstructionType.Unknown, // fist - not in enum
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InstructionType.Unknown, // fistp - not in enum
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InstructionType.Unknown, // ??
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InstructionType.Fld, // fld - 80-bit extended precision
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InstructionType.Unknown, // ??
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InstructionType.Fstp // fstp - 80-bit extended precision
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex DestIndex, FpuRegisterIndex? SrcIndex)> RegisterOperations = new()
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{
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// FCMOVNB ST(0), ST(i)
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{ (RegisterIndex.A, RegisterIndex.A), ("fcmovnb", "st(0), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.C), ("fcmovnb", "st(0), st(1)") },
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{ (RegisterIndex.A, RegisterIndex.D), ("fcmovnb", "st(0), st(2)") },
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{ (RegisterIndex.A, RegisterIndex.B), ("fcmovnb", "st(0), st(3)") },
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{ (RegisterIndex.A, RegisterIndex.Sp), ("fcmovnb", "st(0), st(4)") },
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{ (RegisterIndex.A, RegisterIndex.Bp), ("fcmovnb", "st(0), st(5)") },
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{ (RegisterIndex.A, RegisterIndex.Si), ("fcmovnb", "st(0), st(6)") },
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{ (RegisterIndex.A, RegisterIndex.Di), ("fcmovnb", "st(0), st(7)") },
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{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
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// FCMOVNE ST(0), ST(i)
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{ (RegisterIndex.B, RegisterIndex.A), ("fcmovne", "st(0), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.C), ("fcmovne", "st(0), st(1)") },
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{ (RegisterIndex.B, RegisterIndex.D), ("fcmovne", "st(0), st(2)") },
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{ (RegisterIndex.B, RegisterIndex.B), ("fcmovne", "st(0), st(3)") },
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{ (RegisterIndex.B, RegisterIndex.Sp), ("fcmovne", "st(0), st(4)") },
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{ (RegisterIndex.B, RegisterIndex.Bp), ("fcmovne", "st(0), st(5)") },
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{ (RegisterIndex.B, RegisterIndex.Si), ("fcmovne", "st(0), st(6)") },
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{ (RegisterIndex.B, RegisterIndex.Di), ("fcmovne", "st(0), st(7)") },
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{ (RegisterIndex.B, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.B, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.B, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.B, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.B, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.B, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.B, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.B, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
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// FCMOVNBE ST(0), ST(i)
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{ (RegisterIndex.C, RegisterIndex.A), ("fcmovnbe", "st(0), st(0)") },
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{ (RegisterIndex.C, RegisterIndex.C), ("fcmovnbe", "st(0), st(1)") },
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{ (RegisterIndex.C, RegisterIndex.D), ("fcmovnbe", "st(0), st(2)") },
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{ (RegisterIndex.C, RegisterIndex.B), ("fcmovnbe", "st(0), st(3)") },
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{ (RegisterIndex.C, RegisterIndex.Sp), ("fcmovnbe", "st(0), st(4)") },
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{ (RegisterIndex.C, RegisterIndex.Bp), ("fcmovnbe", "st(0), st(5)") },
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{ (RegisterIndex.C, RegisterIndex.Si), ("fcmovnbe", "st(0), st(6)") },
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{ (RegisterIndex.C, RegisterIndex.Di), ("fcmovnbe", "st(0), st(7)") },
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{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.C, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.C, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.C, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.C, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.C, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.C, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.C, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
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// FCMOVNU ST(0), ST(i)
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{ (RegisterIndex.D, RegisterIndex.A), ("fcmovnu", "st(0), st(0)") },
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{ (RegisterIndex.D, RegisterIndex.C), ("fcmovnu", "st(0), st(1)") },
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{ (RegisterIndex.D, RegisterIndex.D), ("fcmovnu", "st(0), st(2)") },
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{ (RegisterIndex.D, RegisterIndex.B), ("fcmovnu", "st(0), st(3)") },
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{ (RegisterIndex.D, RegisterIndex.Sp), ("fcmovnu", "st(0), st(4)") },
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{ (RegisterIndex.D, RegisterIndex.Bp), ("fcmovnu", "st(0), st(5)") },
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{ (RegisterIndex.D, RegisterIndex.Si), ("fcmovnu", "st(0), st(6)") },
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{ (RegisterIndex.D, RegisterIndex.Di), ("fcmovnu", "st(0), st(7)") },
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{ (RegisterIndex.D, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.D, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.D, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.D, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.D, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.D, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.D, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.D, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
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// Special cases
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{ (RegisterIndex.Si, RegisterIndex.C), ("fclex", "") },
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{ (RegisterIndex.Si, RegisterIndex.D), ("finit", "") },
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{ (RegisterIndex.Si, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, null) }, // fclex
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{ (RegisterIndex.Si, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, null) }, // finit
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// FUCOMI ST(0), ST(i)
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{ (RegisterIndex.Di, RegisterIndex.A), ("fucomi", "st(0), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.C), ("fucomi", "st(0), st(1)") },
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{ (RegisterIndex.Di, RegisterIndex.D), ("fucomi", "st(0), st(2)") },
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{ (RegisterIndex.Di, RegisterIndex.B), ("fucomi", "st(0), st(3)") },
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{ (RegisterIndex.Di, RegisterIndex.Sp), ("fucomi", "st(0), st(4)") },
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{ (RegisterIndex.Di, RegisterIndex.Bp), ("fucomi", "st(0), st(5)") },
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{ (RegisterIndex.Di, RegisterIndex.Si), ("fucomi", "st(0), st(6)") },
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{ (RegisterIndex.Di, RegisterIndex.Di), ("fucomi", "st(0), st(7)") },
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{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
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// FCOMI ST(0), ST(i)
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{ (RegisterIndex.Sp, RegisterIndex.A), ("fcomi", "st(0), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.C), ("fcomi", "st(0), st(1)") },
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{ (RegisterIndex.Sp, RegisterIndex.D), ("fcomi", "st(0), st(2)") },
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{ (RegisterIndex.Sp, RegisterIndex.B), ("fcomi", "st(0), st(3)") },
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{ (RegisterIndex.Sp, RegisterIndex.Sp), ("fcomi", "st(0), st(4)") },
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{ (RegisterIndex.Sp, RegisterIndex.Bp), ("fcomi", "st(0), st(5)") },
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{ (RegisterIndex.Sp, RegisterIndex.Si), ("fcomi", "st(0), st(6)") },
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{ (RegisterIndex.Sp, RegisterIndex.Di), ("fcomi", "st(0), st(7)") }
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{ (RegisterIndex.Sp, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (RegisterIndex.Sp, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
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{ (RegisterIndex.Sp, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
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{ (RegisterIndex.Sp, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
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{ (RegisterIndex.Sp, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
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{ (RegisterIndex.Sp, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
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{ (RegisterIndex.Sp, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
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{ (RegisterIndex.Sp, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) }
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};
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/// <summary>
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/// Initializes a new instance of the LoadStoreInt32Handler class
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/// </summary>
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/// <param name="codeBuffer">The buffer containing the code to decode</param>
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/// <param name="decoder">The instruction decoder that owns this handler</param>
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/// <param name="length">The length of the buffer</param>
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public LoadStoreInt32Handler(byte[] codeBuffer, InstructionDecoder decoder, int length)
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: base(codeBuffer, decoder, length)
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public LoadStoreInt32Handler(InstructionDecoder decoder)
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: base(decoder)
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{
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}
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@ -121,45 +121,65 @@ public class LoadStoreInt32Handler : InstructionHandler
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}
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// Read the ModR/M byte
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var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
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var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
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// Handle based on addressing mode
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if (mod != 3) // Memory operand
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{
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// Set the mnemonic based on the reg field
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instruction.Mnemonic = MemoryMnemonics[(int)reg];
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// Set the instruction type based on the reg field
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instruction.Type = MemoryInstructionTypes[(int)reg];
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// Get the base operand without size prefix
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string baseOperand = memOperand.Replace("dword ptr ", "");
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// Apply the appropriate size prefix based on the operation
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// Set the size based on the operation
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // 32-bit integer operations
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{
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// Keep the dword ptr prefix for integer operations
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instruction.Operands = memOperand;
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// Keep the default 32-bit size
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memoryOperand.Size = 32;
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}
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else if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // 80-bit extended precision operations
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{
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instruction.Operands = $"tword ptr {baseOperand}";
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}
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else
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{
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instruction.Operands = memOperand;
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// Set to 80-bit for extended precision
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memoryOperand.Size = 80;
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}
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// Set the structured operands
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instruction.StructuredOperands =
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[
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memoryOperand
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];
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}
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else // Register operand (ST(i))
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{
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// Look up the register operation in our dictionary
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// Look up the instruction type in the register operations dictionary
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if (RegisterOperations.TryGetValue((reg, rm), out var operation))
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{
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instruction.Mnemonic = operation.Mnemonic;
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instruction.Operands = operation.Operands;
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instruction.Type = operation.Type;
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// Create the FPU register operands
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var destOperand = OperandFactory.CreateFPURegisterOperand(operation.DestIndex);
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// Set the structured operands
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if (operation.SrcIndex.HasValue)
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{
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var srcOperand = OperandFactory.CreateFPURegisterOperand(operation.SrcIndex.Value);
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instruction.StructuredOperands =
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[
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destOperand,
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srcOperand
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];
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}
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else
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{
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instruction.StructuredOperands =
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[
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destOperand
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];
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}
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}
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else
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{
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// Unknown instruction
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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instruction.Type = InstructionType.Unknown;
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instruction.StructuredOperands = [];
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}
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}
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