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split float handlers
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// <summary>
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/// Handler for floating-point load/store float64 operations (DD opcode)
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/// </summary>
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public class LoadStoreFloat64Handler : FloatingPointBaseHandler
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{
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// DD opcode - load/store float64
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private static readonly string[] Mnemonics =
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[
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"fld",
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"??",
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"fst",
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"fstp",
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"frstor",
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"fnsave",
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"fnstsw"
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];
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/// <summary>
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/// Initializes a new instance of the LoadStoreFloat64Handler class
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/// </summary>
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/// <param name="codeBuffer">The buffer containing the code to decode</param>
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/// <param name="decoder">The instruction decoder that owns this handler</param>
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/// <param name="length">The length of the buffer</param>
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public LoadStoreFloat64Handler(byte[] codeBuffer, InstructionDecoder decoder, int length)
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: base(codeBuffer, decoder, length)
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{
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}
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/// <summary>
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/// Checks if this handler can decode the given opcode
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/// </summary>
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/// <param name="opcode">The opcode to check</param>
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/// <returns>True if this handler can decode the opcode</returns>
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public override bool CanHandle(byte opcode)
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{
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return opcode == 0xDD;
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}
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/// <summary>
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/// Decodes a floating-point instruction for load/store float64 operations
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/// </summary>
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/// <param name="opcode">The opcode of the instruction</param>
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/// <param name="instruction">The instruction object to populate</param>
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/// <returns>True if the instruction was successfully decoded</returns>
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public override bool Decode(byte opcode, Instruction instruction)
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{
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int position = Decoder.GetPosition();
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if (position >= Length)
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{
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return false;
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}
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// Read the ModR/M byte
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byte modRM = CodeBuffer[position++];
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Decoder.SetPosition(position);
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// Extract the fields from the ModR/M byte
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byte mod = (byte) ((modRM & 0xC0) >> 6);
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byte reg = (byte) ((modRM & 0x38) >> 3);
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byte rm = (byte) (modRM & 0x07);
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// Set the mnemonic based on the opcode and reg field
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instruction.Mnemonic = Mnemonics[reg];
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// For memory operands, set the operand
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if (mod != 3) // Memory operand
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{
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string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
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if (reg == 0 || reg == 2 || reg == 3) // fld, fst, fstp
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{
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instruction.Operands = $"qword ptr {operand}";
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}
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else // frstor, fnsave, fnstsw
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{
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instruction.Operands = operand;
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}
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}
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else // Register operand (ST(i))
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{
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// Special handling for register-register operations
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if (reg == 0) // FFREE
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{
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instruction.Mnemonic = "ffree";
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instruction.Operands = $"st({rm})";
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}
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else if (reg == 2) // FST
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{
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instruction.Mnemonic = "fst";
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instruction.Operands = $"st({rm})";
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}
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else if (reg == 3) // FSTP
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{
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instruction.Mnemonic = "fstp";
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instruction.Operands = $"st({rm})";
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}
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else if (reg == 4) // FUCOM
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{
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instruction.Mnemonic = "fucom";
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instruction.Operands = $"st({rm})";
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}
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else if (reg == 5) // FUCOMP
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{
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instruction.Mnemonic = "fucomp";
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instruction.Operands = $"st({rm})";
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}
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else
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{
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// Unknown instruction
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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}
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}
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return true;
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}
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}
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