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Code Issues Releases Activity

tests and handler fixes

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This commit is contained in:
bird_egop 2025-04-18 12:49:10 +03:00
parent 4cb20cf741
commit cfef24f72d
16 changed files with 176 additions and 107 deletions
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12
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivStiStHandler.cs
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@ -3,15 +3,15 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint.Arithmetic;
using X86Disassembler.X86.Operands;
/// <summary>
/// Handler for FDIVR ST(i), ST instruction (DC F8-FF)
/// Handler for FDIV ST(i), ST instruction (DC F8-FF)
/// </summary>
public class FdivrStiStHandler_FDIVStiSt : InstructionHandler
public class FdivStiStHandler : InstructionHandler
{
/// <summary>
/// Initializes a new instance of the FdivrStiStHandler class
/// </summary>
/// <param name="decoder">The instruction decoder that owns this handler</param>
public FdivrStiStHandler_FDIVStiSt(InstructionDecoder decoder)
public FdivStiStHandler(InstructionDecoder decoder)
: base(decoder)
{
}
@ -23,7 +23,7 @@ public class FdivrStiStHandler_FDIVStiSt : InstructionHandler
/// <returns>True if this handler can decode the opcode</returns>
public override bool CanHandle(byte opcode)
{
// FDIVR ST(i), ST is DC F8-FF
// FDIV ST(i), ST is DC F8-FF
if (opcode != 0xDC) return false;
if (!Decoder.CanReadByte())
@ -39,7 +39,7 @@ public class FdivrStiStHandler_FDIVStiSt : InstructionHandler
}
/// <summary>
/// Decodes a FDIVR ST(i), ST instruction
/// Decodes a FDIV ST(i), ST instruction
/// </summary>
/// <param name="opcode">The opcode of the instruction</param>
/// <param name="instruction">The instruction object to populate</param>
@ -55,7 +55,7 @@ public class FdivrStiStHandler_FDIVStiSt : InstructionHandler
var stIndex = (FpuRegisterIndex)(Decoder.ReadByte() - 0xF8);
// Set the instruction type
instruction.Type = InstructionType.Fdivr;
instruction.Type = InstructionType.Fdiv;
// Create the FPU register operands
var stiOperand = OperandFactory.CreateFPURegisterOperand(stIndex);

12
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivpStiStHandler.cs
View File

@ -3,15 +3,15 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint.Arithmetic;
using X86Disassembler.X86.Operands;
/// <summary>
/// Handler for FDIVRP ST(i), ST instruction (DE F8-FF)
/// Handler for FDIVP ST(i), ST instruction (DE F8-FF)
/// </summary>
public class FdivrpStiStHandler_FDIVPStiSt : InstructionHandler
public class FdivpStiStHandler : InstructionHandler
{
/// <summary>
/// Initializes a new instance of the FdivrpStiStHandler class
/// </summary>
/// <param name="decoder">The instruction decoder that owns this handler</param>
public FdivrpStiStHandler_FDIVPStiSt(InstructionDecoder decoder)
public FdivpStiStHandler(InstructionDecoder decoder)
: base(decoder)
{
}
@ -23,7 +23,7 @@ public class FdivrpStiStHandler_FDIVPStiSt : InstructionHandler
/// <returns>True if this handler can decode the opcode</returns>
public override bool CanHandle(byte opcode)
{
// FDIVRP ST(i), ST is DE F8-FF
// FDIVP ST(i), ST is DE F8-FF
if (opcode != 0xDE) return false;
if (!Decoder.CanReadByte())
@ -39,7 +39,7 @@ public class FdivrpStiStHandler_FDIVPStiSt : InstructionHandler
}
/// <summary>
/// Decodes a FDIVRP ST(i), ST instruction
/// Decodes a FDIVP ST(i), ST instruction
/// </summary>
/// <param name="opcode">The opcode of the instruction</param>
/// <param name="instruction">The instruction object to populate</param>
@ -55,7 +55,7 @@ public class FdivrpStiStHandler_FDIVPStiSt : InstructionHandler
var stIndex = (FpuRegisterIndex)(Decoder.ReadByte() - 0xF8);
// Set the instruction type
instruction.Type = InstructionType.Fdivrp;
instruction.Type = InstructionType.Fdivp;
// Create the FPU register operands
var stiOperand = OperandFactory.CreateFPURegisterOperand(stIndex);

12
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivrStiStHandler.cs
View File

@ -3,15 +3,15 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint.Arithmetic;
using X86Disassembler.X86.Operands;
/// <summary>
/// Handler for FDIV ST(i), ST instruction (DC F0-F7)
/// Handler for FDIVR ST(i), ST instruction (DC F0-F7)
/// </summary>
public class FdivStiStHandler_FDIVRStiSt : InstructionHandler
public class FdivrStiStHandler : InstructionHandler
{
/// <summary>
/// Initializes a new instance of the FdivStiStHandler class
/// </summary>
/// <param name="decoder">The instruction decoder that owns this handler</param>
public FdivStiStHandler_FDIVRStiSt(InstructionDecoder decoder)
public FdivrStiStHandler(InstructionDecoder decoder)
: base(decoder)
{
}
@ -23,7 +23,7 @@ public class FdivStiStHandler_FDIVRStiSt : InstructionHandler
/// <returns>True if this handler can decode the opcode</returns>
public override bool CanHandle(byte opcode)
{
// FDIV ST(i), ST is DC F0-F7
// FDIVR ST(i), ST is DC F0-F7
if (opcode != 0xDC) return false;
if (!Decoder.CanReadByte())
@ -39,7 +39,7 @@ public class FdivStiStHandler_FDIVRStiSt : InstructionHandler
}
/// <summary>
/// Decodes a FDIV ST(i), ST instruction
/// Decodes a FDIVR ST(i), ST instruction
/// </summary>
/// <param name="opcode">The opcode of the instruction</param>
/// <param name="instruction">The instruction object to populate</param>
@ -55,7 +55,7 @@ public class FdivStiStHandler_FDIVRStiSt : InstructionHandler
var stIndex = (FpuRegisterIndex)(Decoder.ReadByte() - 0xF0);
// Set the instruction type
instruction.Type = InstructionType.Fdiv;
instruction.Type = InstructionType.Fdivr;
// Create the FPU register operands
var stiOperand = OperandFactory.CreateFPURegisterOperand(stIndex);

12
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivrpStiStHandler.cs
View File

@ -3,15 +3,15 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint.Arithmetic;
using X86Disassembler.X86.Operands;
/// <summary>
/// Handler for FDIVP ST(i), ST instruction (DE F0-F7)
/// Handler for FDIVRP ST(i), ST instruction (DE F0-F7)
/// </summary>
public class FdivpStiStHandler_FDIVRPStiSt : InstructionHandler
public class FdivrpStiStHandler : InstructionHandler
{
/// <summary>
/// Initializes a new instance of the FdivpStiStHandler class
/// </summary>
/// <param name="decoder">The instruction decoder that owns this handler</param>
public FdivpStiStHandler_FDIVRPStiSt(InstructionDecoder decoder)
public FdivrpStiStHandler(InstructionDecoder decoder)
: base(decoder)
{
}
@ -23,7 +23,7 @@ public class FdivpStiStHandler_FDIVRPStiSt : InstructionHandler
/// <returns>True if this handler can decode the opcode</returns>
public override bool CanHandle(byte opcode)
{
// FDIVP ST(i), ST is DE F0-F7
// FDIVRP ST(i), ST is DE F0-F7
if (opcode != 0xDE) return false;
if (!Decoder.CanReadByte())
@ -39,7 +39,7 @@ public class FdivpStiStHandler_FDIVRPStiSt : InstructionHandler
}
/// <summary>
/// Decodes a FDIVP ST(i), ST instruction
/// Decodes a FDIVRP ST(i), ST instruction
/// </summary>
/// <param name="opcode">The opcode of the instruction</param>
/// <param name="instruction">The instruction object to populate</param>
@ -55,7 +55,7 @@ public class FdivpStiStHandler_FDIVRPStiSt : InstructionHandler
var stIndex = (FpuRegisterIndex)(Decoder.ReadByte() - 0xF0);
// Set the instruction type
instruction.Type = InstructionType.Fdivp;
instruction.Type = InstructionType.Fdivrp;
// Create the FPU register operands
var stiOperand = OperandFactory.CreateFPURegisterOperand(stIndex);

116
X86Disassembler/X86/Handlers/FloatingPoint/Control/FstswHandler.cs Normal file
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@ -0,0 +1,116 @@
using X86Disassembler.X86.Operands;
namespace X86Disassembler.X86.Handlers.FloatingPoint.Control;
/// <summary>
/// Handler for FSTSW instruction (with WAIT prefix 0x9B)
/// Handles both:
/// - FSTSW AX (0x9B 0xDF 0xE0)
/// - FSTSW m2byte (0x9B 0xDD /7)
/// </summary>
public class FstswHandler : InstructionHandler
{
/// <summary>
/// Initializes a new instance of the FstswHandler class
/// </summary>
/// <param name="decoder">The instruction decoder that owns this handler</param>
public FstswHandler(InstructionDecoder decoder)
: base(decoder)
{
}
/// <summary>
/// Checks if this handler can decode the given opcode
/// </summary>
/// <param name="opcode">The opcode to check</param>
/// <returns>True if this handler can decode the opcode</returns>
public override bool CanHandle(byte opcode)
{
// FSTSW starts with the WAIT prefix (0x9B)
if (opcode != 0x9B) return false;
// Check if we can read the next byte
if (!Decoder.CanReadByte())
return false;
// Check if the next byte is 0xDF (for FSTSW AX) or 0xDD (for FSTSW m2byte)
var (nextByte, modRM) = Decoder.PeakTwoBytes();
if (nextByte != 0xDF && nextByte != 0xDD)
return false;
if (nextByte == 0xDF)
{
// For FSTSW AX, check if we can peek at the third byte and it's 0xE0
return modRM == 0xE0;
}
else // nextByte == 0xDD
{
// For FSTSW m2byte, check if we can peek at ModR/M byte and reg field = 7
byte regField = ModRMDecoder.GetRegFromModRM(modRM);
// The reg field must be 7 for FSTSW m2byte
return regField == 7;
}
}
/// <summary>
/// Decodes an FSTSW instruction
/// </summary>
/// <param name="opcode">The opcode of the instruction</param>
/// <param name="instruction">The instruction object to populate</param>
/// <returns>True if the instruction was successfully decoded</returns>
public override bool Decode(byte opcode, Instruction instruction)
{
// Skip the WAIT prefix (0x9B) - we already read it in CanHandle
if (!Decoder.CanReadByte())
return false;
// Read the second byte (0xDF for AX variant, 0xDD for memory variant)
byte secondByte = Decoder.ReadByte();
// Set the instruction type
instruction.Type = InstructionType.Fstsw;
if (secondByte == 0xDF)
{
// FSTSW AX variant
// Read the 0xE0 byte
if (!Decoder.CanReadByte())
return false;
byte e0Byte = Decoder.ReadByte();
if (e0Byte != 0xE0)
return false;
// Create the AX register operand
var axOperand = OperandFactory.CreateRegisterOperand(RegisterIndex.A, 16);
// Set the structured operands
instruction.StructuredOperands =
[
axOperand
];
}
else if (secondByte == 0xDD)
{
// FSTSW m2byte variant
// Use ModRMDecoder to read and decode the ModR/M byte for 16-bit memory operand
var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM16();
// Set the structured operands
instruction.StructuredOperands =
[
memoryOperand
];
}
else
{
return false;
}
return true;
}
}

28
X86Disassembler/X86/Handlers/FloatingPoint/LoadStore/FildInt64Handler.cs
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@ -54,39 +54,15 @@ public class FildInt64Handler : InstructionHandler
}
// Read the ModR/M byte
var (mod, reg, rm, rawMemoryOperand) = ModRMDecoder.ReadModRM();
var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM64();
// Set the instruction type
instruction.Type = InstructionType.Fild;
// Create a 64-bit memory operand
Operand memoryOperand;
if (rawMemoryOperand is DirectMemoryOperand directMemory)
{
memoryOperand = OperandFactory.CreateDirectMemoryOperand(directMemory.Address, 64);
}
else if (rawMemoryOperand is BaseRegisterMemoryOperand baseMemory)
{
memoryOperand = OperandFactory.CreateBaseRegisterMemoryOperand(baseMemory.BaseRegister, 64);
}
else if (rawMemoryOperand is DisplacementMemoryOperand dispMemory)
{
memoryOperand = OperandFactory.CreateDisplacementMemoryOperand(dispMemory.BaseRegister, dispMemory.Displacement, 64);
}
else if (rawMemoryOperand is ScaledIndexMemoryOperand scaledMemory)
{
memoryOperand = OperandFactory.CreateScaledIndexMemoryOperand(scaledMemory.IndexRegister, scaledMemory.Scale, scaledMemory.BaseRegister, scaledMemory.Displacement, 64);
}
else
{
memoryOperand = rawMemoryOperand;
}
// Set the structured operands
instruction.StructuredOperands =
[
memoryOperand
operand
];
return true;

28
X86Disassembler/X86/Handlers/FloatingPoint/LoadStore/FistpInt64Handler.cs
View File

@ -54,39 +54,15 @@ public class FistpInt64Handler : InstructionHandler
}
// Read the ModR/M byte
var (mod, reg, rm, rawMemoryOperand) = ModRMDecoder.ReadModRM();
var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM64();
// Set the instruction type
instruction.Type = InstructionType.Fistp;
// Create a 64-bit memory operand
Operand memoryOperand;
if (rawMemoryOperand is DirectMemoryOperand directMemory)
{
memoryOperand = OperandFactory.CreateDirectMemoryOperand(directMemory.Address, 64);
}
else if (rawMemoryOperand is BaseRegisterMemoryOperand baseMemory)
{
memoryOperand = OperandFactory.CreateBaseRegisterMemoryOperand(baseMemory.BaseRegister, 64);
}
else if (rawMemoryOperand is DisplacementMemoryOperand dispMemory)
{
memoryOperand = OperandFactory.CreateDisplacementMemoryOperand(dispMemory.BaseRegister, dispMemory.Displacement, 64);
}
else if (rawMemoryOperand is ScaledIndexMemoryOperand scaledMemory)
{
memoryOperand = OperandFactory.CreateScaledIndexMemoryOperand(scaledMemory.IndexRegister, scaledMemory.Scale, scaledMemory.BaseRegister, scaledMemory.Displacement, 64);
}
else
{
memoryOperand = rawMemoryOperand;
}
// Set the structured operands
instruction.StructuredOperands =
[
memoryOperand
operand
];
return true;

2
X86Disassembler/X86/Handlers/FloatingPoint/LoadStore/FldFloat64Handler.cs
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@ -52,7 +52,7 @@ public class FldFloat64Handler : InstructionHandler
}
// Read the ModR/M byte using the specialized FPU method
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu();
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64();
// Verify reg field is 0 (FLD)
if (reg != 0)

2
X86Disassembler/X86/Handlers/FloatingPoint/LoadStore/FstFloat64Handler.cs
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@ -52,7 +52,7 @@ public class FstFloat64Handler : InstructionHandler
}
// Read the ModR/M byte using the specialized FPU method
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu();
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64();
// Set the instruction type
instruction.Type = InstructionType.Fst;

2
X86Disassembler/X86/Handlers/FloatingPoint/LoadStore/FstpFloat64Handler.cs
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@ -52,7 +52,7 @@ public class FstpFloat64Handler : InstructionHandler
}
// Read the ModR/M byte using the specialized FPU method
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu();
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64();
// Set the instruction type
instruction.Type = InstructionType.Fstp;

1
X86Disassembler/X86/Handlers/InstructionHandlerFactory.cs
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@ -418,6 +418,7 @@ public class InstructionHandlerFactory
// Other floating point handlers
_handlers.Add(new FloatingPoint.Control.FnstswHandler(_decoder)); // FNSTSW AX (DF E0)
_handlers.Add(new FloatingPoint.Control.FstswHandler(_decoder)); // FSTSW AX (9B DF E0)
// DB opcode handlers (int32 operations and extended precision)
_handlers.Add(new FloatingPoint.LoadStore.FildInt32Handler(_decoder)); // FILD int32 (DB /0)

8
X86DisassemblerTests/TestData/fdiv_tests.csv
View File

@ -26,8 +26,8 @@ DCFF;[{ "Type": "Fdiv", "Operands": ["ST(7)", "ST(0)"] }]
# Memory operands
D8342510000000;[{ "Type": "Fdiv", "Operands": ["dword ptr [0x10]"] }]
DC342510000000;[{ "Type": "Fdiv", "Operands": ["qword ptr [0x10]"] }]
D83425;[{ "Type": "Fdiv", "Operands": ["dword ptr [eax]"] }]
DC3425;[{ "Type": "Fdiv", "Operands": ["qword ptr [eax]"] }]
D830;[{ "Type": "Fdiv", "Operands": ["dword ptr [eax]"] }]
DC30;[{ "Type": "Fdiv", "Operands": ["qword ptr [eax]"] }]
# FDIVP - Divide floating point values and pop
DEF8;[{ "Type": "Fdivp", "Operands": ["ST(0)", "ST(0)"] }]
@ -42,5 +42,5 @@ DEFF;[{ "Type": "Fdivp", "Operands": ["ST(7)", "ST(0)"] }]
# FIDIV - Divide integer by floating point
DA342510000000;[{ "Type": "Fidiv", "Operands": ["dword ptr [0x10]"] }]
DE342510000000;[{ "Type": "Fidiv", "Operands": ["word ptr [0x10]"] }]
DA3425;[{ "Type": "Fidiv", "Operands": ["dword ptr [eax]"] }]
DE3425;[{ "Type": "Fidiv", "Operands": ["word ptr [eax]"] }]
DA30;[{ "Type": "Fidiv", "Operands": ["dword ptr [eax]"] }]
DE30;[{ "Type": "Fidiv", "Operands": ["word ptr [eax]"] }]

Can't render this file because it contains an unexpected character in line 7 and column 9.

8
X86DisassemblerTests/TestData/fdivr_tests.csv
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@ -26,8 +26,8 @@ DCF7;[{ "Type": "Fdivr", "Operands": ["ST(7)", "ST(0)"] }]
# Memory operands
D83C2510000000;[{ "Type": "Fdivr", "Operands": ["dword ptr [0x10]"] }]
DC3C2510000000;[{ "Type": "Fdivr", "Operands": ["qword ptr [0x10]"] }]
D83C25;[{ "Type": "Fdivr", "Operands": ["dword ptr [eax]"] }]
DC3C25;[{ "Type": "Fdivr", "Operands": ["qword ptr [eax]"] }]
D838;[{ "Type": "Fdivr", "Operands": ["dword ptr [eax]"] }]
DC38;[{ "Type": "Fdivr", "Operands": ["qword ptr [eax]"] }]
# FDIVRP - Divide floating point values (reversed) and pop
DEF0;[{ "Type": "Fdivrp", "Operands": ["ST(0)", "ST(0)"] }]
@ -42,5 +42,5 @@ DEF7;[{ "Type": "Fdivrp", "Operands": ["ST(7)", "ST(0)"] }]
# FIDIVR - Divide floating point by integer (reversed)
DA3C2510000000;[{ "Type": "Fidivr", "Operands": ["dword ptr [0x10]"] }]
DE3C2510000000;[{ "Type": "Fidivr", "Operands": ["word ptr [0x10]"] }]
DA3C25;[{ "Type": "Fidivr", "Operands": ["dword ptr [eax]"] }]
DE3C25;[{ "Type": "Fidivr", "Operands": ["word ptr [eax]"] }]
DA38;[{ "Type": "Fidivr", "Operands": ["dword ptr [eax]"] }]
DE38;[{ "Type": "Fidivr", "Operands": ["word ptr [eax]"] }]

Can't render this file because it contains an unexpected character in line 7 and column 9.

28
X86DisassemblerTests/TestData/fld_fst_tests.csv
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@ -15,17 +15,17 @@ D9C7;[{ "Type": "Fld", "Operands": ["ST(7)"] }]
# Memory operands
D9042510000000;[{ "Type": "Fld", "Operands": ["dword ptr [0x10]"] }]
DD042510000000;[{ "Type": "Fld", "Operands": ["qword ptr [0x10]"] }]
DB2C25;[{ "Type": "Fld", "Operands": ["tbyte ptr [eax]"] }]
D90425;[{ "Type": "Fld", "Operands": ["dword ptr [eax]"] }]
DD0425;[{ "Type": "Fld", "Operands": ["qword ptr [eax]"] }]
DB00;[{ "Type": "Fild", "Operands": ["dword ptr [eax]"] }]
D900;[{ "Type": "Fld", "Operands": ["dword ptr [eax]"] }]
DD00;[{ "Type": "Fld", "Operands": ["qword ptr [eax]"] }]
# With segment override prefixes
26D90425;[{ "Type": "Fld", "Operands": ["dword ptr es:[eax]"] }]
2ED90425;[{ "Type": "Fld", "Operands": ["dword ptr cs:[eax]"] }]
36D90425;[{ "Type": "Fld", "Operands": ["dword ptr ss:[eax]"] }]
3ED90425;[{ "Type": "Fld", "Operands": ["dword ptr ds:[eax]"] }]
64D90425;[{ "Type": "Fld", "Operands": ["dword ptr fs:[eax]"] }]
65D90425;[{ "Type": "Fld", "Operands": ["dword ptr gs:[eax]"] }]
26D900;[{ "Type": "Fld", "Operands": ["dword ptr es:[eax]"] }]
2ED900;[{ "Type": "Fld", "Operands": ["dword ptr cs:[eax]"] }]
36D900;[{ "Type": "Fld", "Operands": ["dword ptr ss:[eax]"] }]
3ED900;[{ "Type": "Fld", "Operands": ["dword ptr ds:[eax]"] }]
64D900;[{ "Type": "Fld", "Operands": ["dword ptr fs:[eax]"] }]
65D900;[{ "Type": "Fld", "Operands": ["dword ptr gs:[eax]"] }]
# FST - Store floating point value
D9D0;[{ "Type": "Fst", "Operands": ["ST(0)"] }]
@ -40,8 +40,8 @@ D9D7;[{ "Type": "Fst", "Operands": ["ST(7)"] }]
# Memory operands
D9142510000000;[{ "Type": "Fst", "Operands": ["dword ptr [0x10]"] }]
DD142510000000;[{ "Type": "Fst", "Operands": ["qword ptr [0x10]"] }]
D91425;[{ "Type": "Fst", "Operands": ["dword ptr [eax]"] }]
DD1425;[{ "Type": "Fst", "Operands": ["qword ptr [eax]"] }]
D910;[{ "Type": "Fst", "Operands": ["dword ptr [eax]"] }]
DD10;[{ "Type": "Fst", "Operands": ["qword ptr [eax]"] }]
# FSTP - Store floating point value and pop
D9D8;[{ "Type": "Fstp", "Operands": ["ST(0)"] }]
@ -56,6 +56,6 @@ D9DF;[{ "Type": "Fstp", "Operands": ["ST(7)"] }]
# Memory operands
D91C2510000000;[{ "Type": "Fstp", "Operands": ["dword ptr [0x10]"] }]
DD1C2510000000;[{ "Type": "Fstp", "Operands": ["qword ptr [0x10]"] }]
DB3C25;[{ "Type": "Fstp", "Operands": ["tbyte ptr [eax]"] }]
D91C25;[{ "Type": "Fstp", "Operands": ["dword ptr [eax]"] }]
DD1C25;[{ "Type": "Fstp", "Operands": ["qword ptr [eax]"] }]
DB18;[{ "Type": "Fistp", "Operands": ["dword ptr [eax]"] }]
D918;[{ "Type": "Fstp", "Operands": ["dword ptr [eax]"] }]
DD18;[{ "Type": "Fstp", "Operands": ["qword ptr [eax]"] }]

Can't render this file because it contains an unexpected character in line 6 and column 9.

8
X86DisassemblerTests/TestData/fmul_tests.csv
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@ -26,8 +26,8 @@ DCCF;[{ "Type": "Fmul", "Operands": ["ST(7)", "ST(0)"] }]
# Memory operands
D80C2510000000;[{ "Type": "Fmul", "Operands": ["dword ptr [0x10]"] }]
DC0C2510000000;[{ "Type": "Fmul", "Operands": ["qword ptr [0x10]"] }]
D80C25;[{ "Type": "Fmul", "Operands": ["dword ptr [eax]"] }]
DC0C25;[{ "Type": "Fmul", "Operands": ["qword ptr [eax]"] }]
D808;[{ "Type": "Fmul", "Operands": ["dword ptr [eax]"] }]
DC08;[{ "Type": "Fmul", "Operands": ["qword ptr [eax]"] }]
# FMULP - Multiply floating point values and pop
DEC8;[{ "Type": "Fmulp", "Operands": ["ST(0)", "ST(0)"] }]
@ -42,5 +42,5 @@ DECF;[{ "Type": "Fmulp", "Operands": ["ST(7)", "ST(0)"] }]
# FIMUL - Multiply integer with floating point
DA0C2510000000;[{ "Type": "Fimul", "Operands": ["dword ptr [0x10]"] }]
DE0C2510000000;[{ "Type": "Fimul", "Operands": ["word ptr [0x10]"] }]
DA0C25;[{ "Type": "Fimul", "Operands": ["dword ptr [eax]"] }]
DE0C25;[{ "Type": "Fimul", "Operands": ["word ptr [eax]"] }]
DA08;[{ "Type": "Fimul", "Operands": ["dword ptr [eax]"] }]
DE08;[{ "Type": "Fimul", "Operands": ["word ptr [eax]"] }]

Can't render this file because it contains an unexpected character in line 7 and column 9.

4
X86DisassemblerTests/TestData/misc_tests.csv
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@ -32,8 +32,8 @@ F4;[{ "Type": "Hlt", "Operands": [] }]
# WAIT/FWAIT - Wait
9B;[{ "Type": "Wait", "Operands": [] }]
# LOCK prefix
F0;[{ "Type": "Lock", "Operands": [] }]
# TODO: LOCK prefix
# F0;[{ "Type": "Lock", "Operands": [] }]
# IN - Input from Port
E410;[{ "Type": "In", "Operands": ["al", "0x10"] }]

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