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https://github.com/sampletext32/ParkanPlayground.git
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Simplified LoadStoreInt16Handler by replacing complex logic with a dictionary-based approach and improving memory operand handling
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bird_egop
@@ -5,18 +5,57 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// </summary>
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/// </summary>
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public class LoadStoreInt16Handler : InstructionHandler
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public class LoadStoreInt16Handler : InstructionHandler
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{
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{
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// DF opcode - load/store int16, misc
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// Memory operand mnemonics for DF opcode - load/store int16, misc
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private static readonly string[] Mnemonics =
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private static readonly string[] MemoryMnemonics =
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[
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[
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"fild",
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"fild", // 0 - 16-bit integer
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"??",
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"??", // 1
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"fist",
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"fist", // 2 - 16-bit integer
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"fistp",
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"fistp", // 3 - 16-bit integer
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"fbld",
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"fbld", // 4 - 80-bit packed BCD
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"fild",
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"fild", // 5 - 64-bit integer
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"fbstp",
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"fbstp", // 6 - 80-bit packed BCD
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"fistp"
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"fistp" // 7 - 64-bit integer
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];
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
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{
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// FFREEP ST(i)
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{ (RegisterIndex.A, RegisterIndex.A), ("ffreep", "st(0)") },
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{ (RegisterIndex.A, RegisterIndex.C), ("ffreep", "st(1)") },
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{ (RegisterIndex.A, RegisterIndex.D), ("ffreep", "st(2)") },
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{ (RegisterIndex.A, RegisterIndex.B), ("ffreep", "st(3)") },
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{ (RegisterIndex.A, RegisterIndex.Sp), ("ffreep", "st(4)") },
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{ (RegisterIndex.A, RegisterIndex.Bp), ("ffreep", "st(5)") },
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{ (RegisterIndex.A, RegisterIndex.Si), ("ffreep", "st(6)") },
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{ (RegisterIndex.A, RegisterIndex.Di), ("ffreep", "st(7)") },
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// Special cases
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{ (RegisterIndex.B, RegisterIndex.A), ("fxch", "") },
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{ (RegisterIndex.C, RegisterIndex.A), ("fstp", "st(1)") },
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{ (RegisterIndex.D, RegisterIndex.A), ("fstp", "st(1)") },
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// FUCOMIP ST(0), ST(i)
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{ (RegisterIndex.Di, RegisterIndex.A), ("fucomip", "st(0), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.C), ("fucomip", "st(0), st(1)") },
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{ (RegisterIndex.Di, RegisterIndex.D), ("fucomip", "st(0), st(2)") },
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{ (RegisterIndex.Di, RegisterIndex.B), ("fucomip", "st(0), st(3)") },
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{ (RegisterIndex.Di, RegisterIndex.Sp), ("fucomip", "st(0), st(4)") },
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{ (RegisterIndex.Di, RegisterIndex.Bp), ("fucomip", "st(0), st(5)") },
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{ (RegisterIndex.Di, RegisterIndex.Si), ("fucomip", "st(0), st(6)") },
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{ (RegisterIndex.Di, RegisterIndex.Di), ("fucomip", "st(0), st(7)") },
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// FCOMIP ST(0), ST(i)
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{ (RegisterIndex.Sp, RegisterIndex.A), ("fcomip", "st(0), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.C), ("fcomip", "st(0), st(1)") },
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{ (RegisterIndex.Sp, RegisterIndex.D), ("fcomip", "st(0), st(2)") },
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{ (RegisterIndex.Sp, RegisterIndex.B), ("fcomip", "st(0), st(3)") },
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{ (RegisterIndex.Sp, RegisterIndex.Sp), ("fcomip", "st(0), st(4)") },
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{ (RegisterIndex.Sp, RegisterIndex.Bp), ("fcomip", "st(0), st(5)") },
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{ (RegisterIndex.Sp, RegisterIndex.Si), ("fcomip", "st(0), st(6)") },
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{ (RegisterIndex.Sp, RegisterIndex.Di), ("fcomip", "st(0), st(7)") }
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};
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/// <summary>
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/// <summary>
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/// Initializes a new instance of the LoadStoreInt16Handler class
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/// Initializes a new instance of the LoadStoreInt16Handler class
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@@ -47,15 +86,13 @@ public class LoadStoreInt16Handler : InstructionHandler
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/// <returns>True if the instruction was successfully decoded</returns>
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/// <returns>True if the instruction was successfully decoded</returns>
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public override bool Decode(byte opcode, Instruction instruction)
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public override bool Decode(byte opcode, Instruction instruction)
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{
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{
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int position = Decoder.GetPosition();
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if (!Decoder.CanReadByte())
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if (position >= Length)
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{
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{
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return false;
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return false;
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}
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}
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// Read the ModR/M byte
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// Read the ModR/M byte
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var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
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var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
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// Check for FNSTSW AX (DF E0)
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// Check for FNSTSW AX (DF E0)
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if (mod == 3 && reg == RegisterIndex.Bp && rm == RegisterIndex.A)
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if (mod == 3 && reg == RegisterIndex.Bp && rm == RegisterIndex.A)
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@@ -64,78 +101,40 @@ public class LoadStoreInt16Handler : InstructionHandler
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return false;
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return false;
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}
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}
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// Set the mnemonic based on the opcode and reg field
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// Handle based on addressing mode
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instruction.Mnemonic = Mnemonics[(int)reg];
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// For memory operands, set the operand
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if (mod != 3) // Memory operand
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if (mod != 3) // Memory operand
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{
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{
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string operand = ModRMDecoder.DecodeModRM(mod, rm, false);
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// Set the mnemonic based on the reg field
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instruction.Mnemonic = MemoryMnemonics[(int)reg];
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D || reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // fild, fist, fistp, fild, fistp
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// Get the base operand without size prefix
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string baseOperand = memOperand.Replace("dword ptr ", "");
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// Apply the appropriate size prefix based on the operation
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if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // 16-bit integer operations
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{
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{
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if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // 64-bit integer
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instruction.Operands = $"word ptr {baseOperand}";
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{
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// Replace dword ptr with qword ptr for 64-bit integers
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operand = operand.Replace("dword ptr", "qword ptr");
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instruction.Operands = operand;
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}
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else // 16-bit integer
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{
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// Replace dword ptr with word ptr for 16-bit integers
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operand = operand.Replace("dword ptr", "word ptr");
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instruction.Operands = operand;
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}
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}
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}
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else if (reg == RegisterIndex.Si || reg == RegisterIndex.Sp) // fbld, fbstp
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else if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // 64-bit integer operations
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{
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{
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// Replace dword ptr with tbyte ptr for 80-bit packed BCD
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instruction.Operands = $"qword ptr {baseOperand}";
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operand = operand.Replace("dword ptr", "tbyte ptr");
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instruction.Operands = operand;
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}
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}
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else
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else if (reg == RegisterIndex.Si || reg == RegisterIndex.Sp) // 80-bit packed BCD operations
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{
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{
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instruction.Operands = operand;
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instruction.Operands = $"tbyte ptr {baseOperand}";
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}
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else // Other operations
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{
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instruction.Operands = memOperand;
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}
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}
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}
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}
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else // Register operand (ST(i))
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else // Register operand (ST(i))
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{
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{
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// Special handling for register-register operations
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// Look up the register operation in our dictionary
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if (reg == RegisterIndex.A) // FFREEP
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if (RegisterOperations.TryGetValue((reg, rm), out var operation))
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{
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{
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instruction.Mnemonic = "ffreep";
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instruction.Mnemonic = operation.Mnemonic;
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instruction.Operands = $"st({(int)rm})";
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instruction.Operands = operation.Operands;
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}
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else if (reg == RegisterIndex.B && rm == RegisterIndex.A) // FXCH
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{
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instruction.Mnemonic = "fxch";
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instruction.Operands = "";
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}
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else if (reg == RegisterIndex.C && rm == RegisterIndex.A) // FSTP
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{
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instruction.Mnemonic = "fstp";
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instruction.Operands = "st(1)";
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}
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else if (reg == RegisterIndex.D && rm == RegisterIndex.A) // FSTP
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{
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instruction.Mnemonic = "fstp";
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instruction.Operands = "st(1)";
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}
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else if (reg == RegisterIndex.Si) // FNSTSW
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{
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// This should not happen as FNSTSW AX is handled by FnstswHandler
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instruction.Mnemonic = "??";
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instruction.Operands = "";
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}
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else if (reg == RegisterIndex.Di) // FUCOMIP
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{
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instruction.Mnemonic = "fucomip";
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instruction.Operands = $"st(0), st({(int)rm})";
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}
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else if (reg == RegisterIndex.Sp) // FCOMIP
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{
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instruction.Mnemonic = "fcomip";
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instruction.Operands = $"st(0), st({(int)rm})";
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}
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}
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else
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else
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{
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{
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