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ParkanPlayground/X86DisassemblerTests/TestData
History
bird_egop 800915b534 new handlers and test fixes
2025-04-16 20:54:08 +03:00
..
adc_tests.csv
Enhanced test coverage for ADC and ADD instructions
2025-04-15 22:27:51 +03:00
add_tests.csv
fix various tests
2025-04-15 23:54:51 +03:00
and_tests.csv
fix various tests
2025-04-15 23:54:51 +03:00
bit_tests.csv
Enhanced test coverage for CMP, BIT and CALL instructions
2025-04-15 22:32:37 +03:00
call_tests.csv
Added detailed comments to test files explaining x86 encoding special cases: 1) Mod=00 and R/M=101 (EBP) for displacement-only addressing, 2) Mod=00 and R/M=100 (ESP) for SIB byte requirement, 3) SIB byte with EBP as base register special cases
2025-04-16 19:58:34 +03:00
cmp_tests.csv
Fixed several instruction handling issues: 1) Added proper handling for zero displacements in memory operands, 2) Fixed large unsigned displacement values display, 3) Added CmpEaxImmHandler for CMP EAX, imm32 instruction, 4) Fixed JP and JNP conditional jump instruction types
2025-04-16 19:43:03 +03:00
div_tests.csv
Fixed several instruction handling issues: 1) Added proper handling for zero displacements in memory operands, 2) Fixed large unsigned displacement values display, 3) Added CmpEaxImmHandler for CMP EAX, imm32 instruction, 4) Fixed JP and JNP conditional jump instruction types
2025-04-16 19:43:03 +03:00
fadd_tests.csv
Split FPU tests by instruction type for better organization and readability
2025-04-15 22:45:46 +03:00
fcom_tests.csv
Split FPU tests by instruction type for better organization and readability
2025-04-15 22:45:46 +03:00
fdiv_tests.csv
Split FPU tests by instruction type for better organization and readability
2025-04-15 22:45:46 +03:00
fdivr_tests.csv
Split FPU tests by instruction type for better organization and readability
2025-04-15 22:45:46 +03:00
flag_tests.csv
Enhanced test coverage for DIV, flag control, and FNSTSW instructions
2025-04-15 22:35:14 +03:00
fld_fst_tests.csv
Split FPU tests by instruction type for better organization and readability
2025-04-15 22:45:46 +03:00
fmul_tests.csv
Split FPU tests by instruction type for better organization and readability
2025-04-15 22:45:46 +03:00
fnstsw_tests.csv
Enhanced test coverage for DIV, flag control, and FNSTSW instructions
2025-04-15 22:35:14 +03:00
fpu_misc_tests.csv
Split FPU tests by instruction type for better organization and readability
2025-04-15 22:45:46 +03:00
fstsw_tests.csv
Split FPU tests by instruction type for better organization and readability
2025-04-15 22:45:46 +03:00
fsub_tests.csv
Split FPU tests by instruction type for better organization and readability
2025-04-15 22:45:46 +03:00
fsubr_tests.csv
Split FPU tests by instruction type for better organization and readability
2025-04-15 22:45:46 +03:00
idiv_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
imul_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
jcc_tests.csv
Fixed several instruction handling issues: 1) Added proper handling for zero displacements in memory operands, 2) Fixed large unsigned displacement values display, 3) Added CmpEaxImmHandler for CMP EAX, imm32 instruction, 4) Fixed JP and JNP conditional jump instruction types
2025-04-16 19:43:03 +03:00
jmp_tests.csv
Fixed invalid test cases in x86 disassembler tests. Added comments explaining special cases in x86 encoding and added valid test cases for LEA with different destination registers.
2025-04-16 20:13:07 +03:00
lea_tests.csv
new handlers and test fixes
2025-04-16 20:54:08 +03:00
misc_tests.csv
Fixed special case in INC/DEC tests with EBP addressing. When Mod=00 and R/M=101 (EBP), it indicates a 32-bit displacement-only addressing mode, not [EBP]. Added correct test cases with Mod=01 and zero displacement.
2025-04-16 20:18:14 +03:00
mov_tests.csv
Fixed special case in MOV tests with EBP addressing. When Mod=00 and R/M=101 (EBP), it indicates a 32-bit displacement-only addressing mode, not [EBP]. Added correct test cases with Mod=01 and zero displacement.
2025-04-16 20:27:00 +03:00
mul_tests.csv
Fixed MUL instruction tests with SIB byte encoding. When using SIB byte with Base=101 (EBP) and Mod=00, it requires a 32-bit displacement. Replaced incorrect encodings with proper ones for [eax] and direct memory addressing.
2025-04-16 20:40:18 +03:00
neg_tests.csv
new handlers and test fixes
2025-04-16 20:54:08 +03:00
nop_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
not_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
or_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
popreg_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
poprm_tests.csv
Fixed invalid test cases in x86 disassembler tests. Added comments explaining special cases in x86 encoding and added valid test cases for LEA with different destination registers.
2025-04-16 20:13:07 +03:00
pushimm_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
pushreg_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
pushrm_tests.csv
Fixed invalid test cases in x86 disassembler tests. Added comments explaining special cases in x86 encoding and added valid test cases for LEA with different destination registers.
2025-04-16 20:13:07 +03:00
rcl_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
rcr_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
ret_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
rol_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
ror_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
sar_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
sbb_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
segment_override_tests.csv
fix segment override tests according to ghidra
2025-04-15 23:22:14 +03:00
shl_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
shr_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
stack_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
string_tests.csv
fix various tests
2025-04-15 23:54:51 +03:00
sub_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
test_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
xchg_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00
xor_tests.csv
add tons of tests
2025-04-15 22:20:46 +03:00