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47 lines
2.5 KiB
CSV
47 lines
2.5 KiB
CSV
# POP r/m32 instruction tests
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# Format: RawBytes;Instructions
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RawBytes;Instructions
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# POP r/m32 (opcode 8F /0) with register operands
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8F00;[{ "Type": "Pop", "Operands": ["dword ptr [eax]"] }]
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8F01;[{ "Type": "Pop", "Operands": ["dword ptr [ecx]"] }]
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8F02;[{ "Type": "Pop", "Operands": ["dword ptr [edx]"] }]
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8F03;[{ "Type": "Pop", "Operands": ["dword ptr [ebx]"] }]
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8F04;[{ "Type": "Pop", "Operands": ["dword ptr [esp]"] }]
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8F05;[{ "Type": "Pop", "Operands": ["dword ptr [ebp]"] }]
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8F06;[{ "Type": "Pop", "Operands": ["dword ptr [esi]"] }]
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8F07;[{ "Type": "Pop", "Operands": ["dword ptr [edi]"] }]
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# POP r/m32 (opcode 8F /0) with memory operands and displacement
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8F4010;[{ "Type": "Pop", "Operands": ["dword ptr [eax+0x10]"] }]
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8F4110;[{ "Type": "Pop", "Operands": ["dword ptr [ecx+0x10]"] }]
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8F4210;[{ "Type": "Pop", "Operands": ["dword ptr [edx+0x10]"] }]
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8F4310;[{ "Type": "Pop", "Operands": ["dword ptr [ebx+0x10]"] }]
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8F4410;[{ "Type": "Pop", "Operands": ["dword ptr [esp+0x10]"] }]
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8F4510;[{ "Type": "Pop", "Operands": ["dword ptr [ebp+0x10]"] }]
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8F4610;[{ "Type": "Pop", "Operands": ["dword ptr [esi+0x10]"] }]
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8F4710;[{ "Type": "Pop", "Operands": ["dword ptr [edi+0x10]"] }]
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# POP r/m32 (opcode 8F /0) with SIB byte
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# SPECIAL CASE: The following encodings with EBP as base register have special rules.
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# When the SIB byte has Base=101 (EBP) and Mod=00, the base register is not used.
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# Instead, a 32-bit displacement follows the SIB byte (similar to the Mod=00, R/M=101 special case).
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# These instructions are commented out because they're invalid without the 32-bit displacement.
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# The correct encoding would include a 32-bit displacement after the SIB byte.
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# 8F04C5;[{ "Type": "Pop", "Operands": ["dword ptr [eax*8+ebp]"] }]
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# 8F04CD;[{ "Type": "Pop", "Operands": ["dword ptr [ecx*8+ebp]"] }]
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# 8F04D5;[{ "Type": "Pop", "Operands": ["dword ptr [edx*8+ebp]"] }]
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# 8F04DD;[{ "Type": "Pop", "Operands": ["dword ptr [ebx*8+ebp]"] }]
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# POP r/m32 (opcode 8F /0) with direct memory operand
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8F0578563412;[{ "Type": "Pop", "Operands": ["dword ptr [0x12345678]"] }]
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# POP r/m32 (opcode 8F /0) with segment override prefixes
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268F4510;[{ "Type": "Pop", "Operands": ["dword ptr es:[ebp+0x10]"] }]
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2E8F4510;[{ "Type": "Pop", "Operands": ["dword ptr cs:[ebp+0x10]"] }]
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368F4510;[{ "Type": "Pop", "Operands": ["dword ptr ss:[ebp+0x10]"] }]
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3E8F4510;[{ "Type": "Pop", "Operands": ["dword ptr ds:[ebp+0x10]"] }]
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648F4510;[{ "Type": "Pop", "Operands": ["dword ptr fs:[ebp+0x10]"] }]
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658F4510;[{ "Type": "Pop", "Operands": ["dword ptr gs:[ebp+0x10]"] }]
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