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| 1 | # SUB instruction tests |
|---|---|
| 2 | # Format: RawBytes;Instructions |
| 3 | RawBytes;Instructions |
| 4 | # Register-to-register SUB (32-bit) |
| 5 | # Register-to-memory SUB (32-bit) |
| 6 | # Memory-to-register SUB (32-bit) |
| 7 | # Immediate-to-register SUB (32-bit immediate) |
| 8 | # Immediate-to-memory SUB (32-bit immediate) |
| 9 | # Small immediate SUB (8-bit immediate to 32-bit register) |
| 10 | # Sign-extended immediate SUB (8-bit immediate sign-extended to 32-bit) |
| 11 | # 8-bit register operations |
| 12 | # SUB r/m8, r8 (opcode 28) |
| 13 | # SUB r8, r/m8 (opcode 2A) |
| 14 | # SUB AL, imm8 (opcode 2C) |
| 15 | # SUB r/m8, imm8 (opcode 80 /5) |
| 16 | # 16-bit register operations with operand size prefix (0x66) |
| 17 | # Note: The disassembler currently outputs 32-bit register names even with 0x66 prefix |
| 18 | # SUB r/m16, r16 (opcode 29 with 0x66 prefix) |
| 19 | # SUB r16, r/m16 (opcode 2B with 0x66 prefix) |
| 20 | # SUB AX, imm16 (opcode 2D with 0x66 prefix) |
| 21 | # SUB r/m16, imm8 (opcode 83 /5 with 0x66 prefix and sign extension) |