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5.4 KiB
5.4 KiB
| 1 | # CALL instruction tests |
|---|---|
| 2 | # Format: RawBytes;Instructions |
| 3 | RawBytes;Instructions |
| 4 | # CALL rel32 (opcode E8) |
| 5 | # CALL r/m32 (opcode FF /2) with register operands |
| 6 | # CALL m32 (opcode FF /2) with memory operands |
| 7 | # SPECIAL CASES in x86 encoding: |
| 8 | # 1. When Mod=00 and R/M=100 (ESP), a SIB byte is required. The instruction FF14 is invalid because |
| 9 | # it's missing the required SIB byte. The correct encoding would use a SIB byte (e.g., FF1424). |
| 10 | # 2. When Mod=00 and R/M=101 (EBP), this doesn't actually refer to [EBP] but instead indicates |
| 11 | # CALL m32 (opcode FF /2) with SIB addressing |
| 12 | # SPECIAL CASE: SIB byte with EBP as base register |
| 13 | # When the SIB byte has Base=101 (EBP) and Mod=00, the base register is not used. |
| 14 | # Instead, a 32-bit displacement follows the SIB byte (similar to the Mod=00, R/M=101 special case). |
| 15 | # This instruction is commented out because it's not correctly recognized by many disassemblers. |
| 16 | # SPECIAL CASE: Another SIB byte with EBP as base register |
| 17 | # When the SIB byte has Base=101 (EBP) and Mod=00, the base register is not used. |
| 18 | # Instead, a 32-bit displacement follows the SIB byte (similar to the Mod=00, R/M=101 special case). |
| 19 | # This instruction is commented out because it's not correctly recognized by many disassemblers. |
| 20 | # CALL m32 (opcode FF /2) with displacement |
| 21 | # CALL m32 (opcode FF /2) with SIB and displacement |
| 22 | # CALL m16:32 (opcode FF /3) - Far call with memory operand |
| 23 | # SPECIAL CASE in x86 encoding: |
| 24 | # When Mod=00 and R/M=101 (EBP), this doesn't actually refer to [EBP] but instead indicates |
| 25 | # CALL m32 (opcode FF /2) with direct memory operand |
| 26 | # CALL m32 (opcode FF /2) with segment override prefixes |