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33 lines
1.1 KiB
CSV
33 lines
1.1 KiB
CSV
# ROR instruction tests
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# Format: RawBytes;Instructions
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RawBytes;Instructions
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# ROR r/m8, 1 (opcode D0 /1)
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D0C8;[{ "Type": "Ror", "Operands": ["al", "0x01"] }]
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D0CB;[{ "Type": "Ror", "Operands": ["bl", "0x01"] }]
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# ROR r/m32, 1 (opcode D1 /1)
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D1C8;[{ "Type": "Ror", "Operands": ["eax", "0x01"] }]
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D1CB;[{ "Type": "Ror", "Operands": ["ebx", "0x01"] }]
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# ROR r/m8, CL (opcode D2 /1)
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D2C8;[{ "Type": "Ror", "Operands": ["al", "cl"] }]
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D2CB;[{ "Type": "Ror", "Operands": ["bl", "cl"] }]
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# ROR r/m32, CL (opcode D3 /1)
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D3C8;[{ "Type": "Ror", "Operands": ["eax", "cl"] }]
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D3CB;[{ "Type": "Ror", "Operands": ["ebx", "cl"] }]
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# ROR r/m8, imm8 (opcode C0 /1)
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C0C805;[{ "Type": "Ror", "Operands": ["al", "0x05"] }]
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C0CB05;[{ "Type": "Ror", "Operands": ["bl", "0x05"] }]
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# ROR r/m32, imm8 (opcode C1 /1)
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C1C805;[{ "Type": "Ror", "Operands": ["eax", "0x05"] }]
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C1CB05;[{ "Type": "Ror", "Operands": ["ebx", "0x05"] }]
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# ROR with memory operands (fixed)
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D04810;[{ "Type": "Ror", "Operands": ["byte ptr [eax+0x10]", "0x01"] }]
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D34810;[{ "Type": "Ror", "Operands": ["dword ptr [eax+0x10]", "cl"] }]
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C1481005;[{ "Type": "Ror", "Operands": ["dword ptr [eax+0x10]", "0x05"] }]
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