mirrors/uv-k5-firmware-custom
0
Fork 0
mirror of https://github.com/OneOfEleven/uv-k5-firmware-custom.git synced 2025-04-28 22:31:25 +03:00
Code Issues Releases Activity

Merge pull request #261 from bricky149/enable-wfi

Browse Source 
Enable MCU power-saving
This commit is contained in:
OneOfEleven 2023-10-28 20:00:51 +01:00 committed by GitHub
commit 059436fdf1
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 32 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
bsp/dp32g030/syscon.h
View File

@ -343,6 +343,23 @@
#define SYSCON_CHIP_ID3_ADDR (SYSCON_BASE_ADDR + 0x008CU) #define SYSCON_CHIP_ID3_ADDR (SYSCON_BASE_ADDR + 0x008CU)
#define SYSCON_CHIP_ID3 (*(volatile uint32_t *)SYSCON_CHIP_ID3_ADDR) #define SYSCON_CHIP_ID3 (*(volatile uint32_t *)SYSCON_CHIP_ID3_ADDR)
#define SYSCON_REGISTER_ADDR (SYSCON_BASE_ADDR + 0x0100U)
#define SYSCON_REGISTER (*(volatile uint32_t *)SYSCON_REGISTER_ADDR)
#define SYSCON_REGISTER_SLEEPONEXIT_SHIFT 1
#define SYSCON_REGISTER_SLEEPONEXIT_WIDTH 1
#define SYSCON_REGISTER_SLEEPONEXIT_MASK (((1U << SYSCON_REGISTER_SLEEPONEXIT_WIDTH) - 1U) << SYSCON_REGISTER_SLEEPONEXIT_SHIFT)
#define SYSCON_REGISTER_SLEEPONEXIT_VALUE_ENABLE 1U
#define SYSCON_REGISTER_SLEEPONEXIT_BITS_ENABLE (SYSCON_REGISTER_SLEEPONEXIT_VALUE_ENABLE << SYSCON_REGISTER_SLEEPONEXIT_SHIFT)
#define SYSCON_REGISTER_SLEEPONEXIT_VALUE_DISABLE 0U
#define SYSCON_REGISTER_SLEEPONEXIT_BITS_DISABLE (SYSCON_REGISTER_SLEEPONEXIT_VALUE_DISABLE << SYSCON_REGISTER_SLEEPONEXIT_SHIFT)
#define SYSCON_REGISTER_SLEEPDEEP_SHIFT 2
#define SYSCON_REGISTER_SLEEPDEEP_WIDTH 1
#define SYSCON_REGISTER_SLEEPDEEP_MASK (((1U << SYSCON_REGISTER_SLEEPDEEP_WIDTH) - 1U) << SYSCON_REGISTER_SLEEPDEEP_SHIFT)
#define SYSCON_REGISTER_SLEEPDEEP_VALUE_ENABLE 1U
#define SYSCON_REGISTER_SLEEPDEEP_BITS_ENABLE (SYSCON_REGISTER_SLEEPDEEP_VALUE_ENABLE << SYSCON_REGISTER_SLEEPDEEP_SHIFT)
#define SYSCON_REGISTER_SLEEPDEEP_VALUE_DISABLE 0U
#define SYSCON_REGISTER_SLEEPDEEP_BITS_DISABLE (SYSCON_REGISTER_SLEEPDEEP_VALUE_DISABLE << SYSCON_REGISTER_SLEEPDEEP_SHIFT)
#endif #endif

1
hardware/dp32g030/syscon.def
View File

@ -176,3 +176,4 @@ CHIP_ID1 = 0x0084
CHIP_ID2 = 0x0088 CHIP_ID2 = 0x0088
CHIP_ID3 = 0x008C CHIP_ID3 = 0x008C
SCR = 0x0100

13
main.c
View File

@ -236,8 +236,21 @@ void Main(void)
#endif #endif
} }
// Everything is initialised, set SLEEP* bits
SYSCON_REGISTER |= SYSCON_REGISTER_SLEEPONEXIT_BITS_ENABLE;
SYSCON_REGISTER |= SYSCON_REGISTER_SLEEPDEEP_BITS_ENABLE;
while (1) while (1)
{ {
// Mask interrupts
__asm volatile ("cpsid i");
if (!g_next_time_slice)
// Idle condition, hint the MCU to sleep
// CMSIS suggests GCC reorders memory and is undesirable
__asm volatile ("wfi":::"memory");
// Unmask interrupts
__asm volatile ("cpsie i");
APP_process(); APP_process();
if (g_next_time_slice) if (g_next_time_slice)