mirror of
https://github.com/OneOfEleven/uv-k5-firmware-custom.git
synced 2025-04-28 06:11:24 +03:00
Fix RF scan problem + removed enums
This commit is contained in:
OneOfEleven
parent
9f3fa510c2
commit
5b5259c17d
2
am_fix.c
2
am_fix.c
@ -451,7 +451,7 @@
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// remember the new table index
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gain_table_index_prev[vfo] = index;
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BK4819_WriteRegister(BK4819_REG_13, gain_table[index].reg_val);
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BK4819_WriteRegister(0x13, gain_table[index].reg_val);
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// offset the RSSI reading to the rest of the firmware to cancel out the gain adjustments we make
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@ -186,21 +186,21 @@ void AIRCOPY_start_fsk_tx(const int request_block_num)
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(0u << 0); // 0 ~ 7 ???
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// set the packet size
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BK4819_WriteRegister(BK4819_REG_5D, (((tx_size * 2) - 1) << 8));
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BK4819_WriteRegister(0x5D, (((tx_size * 2) - 1) << 8));
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// clear TX fifo
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BK4819_WriteRegister(BK4819_REG_59, (1u << 15) | fsk_reg59);
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BK4819_WriteRegister(BK4819_REG_59, fsk_reg59);
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BK4819_WriteRegister(0x59, (1u << 15) | fsk_reg59);
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BK4819_WriteRegister(0x59, fsk_reg59);
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// load the packet
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for (k = 0; k < tx_size; k++)
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BK4819_WriteRegister(BK4819_REG_5F, g_fsk_buffer[k]);
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BK4819_WriteRegister(0x5F, g_fsk_buffer[k]);
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// enable tx interrupt(s)
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BK4819_WriteRegister(BK4819_REG_3F, BK4819_REG_3F_FSK_TX_FINISHED);
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BK4819_WriteRegister(0x3F, BK4819_REG_3F_FSK_TX_FINISHED);
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// enable scramble, enable TX
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BK4819_WriteRegister(BK4819_REG_59, (1u << 13) | (1u << 11) | fsk_reg59);
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BK4819_WriteRegister(0x59, (1u << 13) | (1u << 11) | fsk_reg59);
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}
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void AIRCOPY_stop_fsk_tx(void)
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@ -268,10 +268,10 @@ void AIRCOPY_process_fsk_tx_10ms(void)
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if (--g_fsk_tx_timeout_10ms > 0)
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{ // still TX'ing
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if ((BK4819_ReadRegister(BK4819_REG_0C) & (1u << 0)) == 0)
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if ((BK4819_ReadRegister(0x0C) & (1u << 0)) == 0)
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return;
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BK4819_WriteRegister(BK4819_REG_02, 0);
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interrupt_bits = BK4819_ReadRegister(BK4819_REG_02);
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BK4819_WriteRegister(0x02, 0);
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interrupt_bits = BK4819_ReadRegister(0x02);
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if ((interrupt_bits & BK4819_REG_02_FSK_TX_FINISHED) == 0)
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return; // TX not yet finished
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}
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@ -343,7 +343,7 @@ void AIRCOPY_process_fsk_rx_10ms(void)
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//
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// <2:0> 0 ???
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//
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status = BK4819_ReadRegister(BK4819_REG_59);
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status = BK4819_ReadRegister(0x59);
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if (status & (1u << 11) || g_fsk_tx_timeout_10ms > 0)
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return; // FSK TX is busy
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@ -355,13 +355,13 @@ void AIRCOPY_process_fsk_rx_10ms(void)
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BK4819_start_fsk_rx((g_aircopy_state == AIRCOPY_TX) ? AIRCOPY_REQ_PACKET_SIZE : AIRCOPY_DATA_PACKET_SIZE);
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}
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status = BK4819_ReadRegister(BK4819_REG_0C);
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status = BK4819_ReadRegister(0x0C);
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if ((status & (1u << 0)) == 0)
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return; // no flagged interrupts
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// read the interrupt flags
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BK4819_WriteRegister(BK4819_REG_02, 0); // clear them
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interrupt_bits = BK4819_ReadRegister(BK4819_REG_02);
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BK4819_WriteRegister(0x02, 0); // clear them
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interrupt_bits = BK4819_ReadRegister(0x02);
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if (interrupt_bits & BK4819_REG_02_FSK_RX_SYNC)
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BK4819_set_GPIO_pin(BK4819_GPIO6_PIN2_GREEN, true); // LED on
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@ -377,7 +377,7 @@ void AIRCOPY_process_fsk_rx_10ms(void)
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// fetch RX'ed data
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for (i = 0; i < 4; i++)
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{
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const uint16_t word = BK4819_ReadRegister(BK4819_REG_5F);
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const uint16_t word = BK4819_ReadRegister(0x5F);
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if (g_fsk_write_index < ARRAY_SIZE(g_fsk_buffer))
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g_fsk_buffer[g_fsk_write_index++] = word;
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}
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@ -400,7 +400,7 @@ void AIRCOPY_process_fsk_rx_10ms(void)
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//
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// <3:0> ???
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//
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status = BK4819_ReadRegister(BK4819_REG_0B);
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status = BK4819_ReadRegister(0x0B);
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// check to see if it's a REQ/ACK packet
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if (g_fsk_write_index == req_ack_size)
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@ -591,10 +591,10 @@ send_req:
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while (g_fsk_tx_timeout_10ms-- > 0)
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{
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SYSTEM_DelayMs(5);
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if (BK4819_ReadRegister(BK4819_REG_0C) & (1u << 0))
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if (BK4819_ReadRegister(0x0C) & (1u << 0))
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{ // we have interrupt flags
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BK4819_WriteRegister(BK4819_REG_02, 0);
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const uint16_t interrupt_bits = BK4819_ReadRegister(BK4819_REG_02);
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BK4819_WriteRegister(0x02, 0);
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const uint16_t interrupt_bits = BK4819_ReadRegister(0x02);
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if (interrupt_bits & BK4819_REG_02_FSK_TX_FINISHED)
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g_fsk_tx_timeout_10ms = 0; // TX is complete
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}
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32
app/app.c
32
app/app.c
@ -247,7 +247,21 @@ static void APP_process_rx(void)
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if (g_scan_state_dir != SCAN_STATE_DIR_OFF) // && IS_FREQ_CHANNEL(g_scan_next_channel))
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{
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if (g_squelch_open)
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{
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switch (g_eeprom.scan_resume_mode)
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{
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case SCAN_RESUME_TIME: // stay only for a limited time
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break;
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case SCAN_RESUME_CARRIER: // stay untill the carrier goes away
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g_scan_pause_10ms = g_eeprom.scan_hold_time_500ms * 50;
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g_scan_pause_time_mode = false;
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break;
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case SCAN_RESUME_STOP: // stop scan once we find any signal
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APP_stop_scan();
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break;
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}
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return;
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}
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Mode = END_OF_RX_MODE_END;
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goto Skip;
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@ -284,7 +298,7 @@ static void APP_process_rx(void)
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if (g_squelch_open)
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{
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if (g_setting_backlight_on_tx_rx >= 2)
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backlight_turn_on(backlight_tx_rx_time_500ms);
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backlight_turn_on(backlight_tx_rx_time_500ms); // keep the backlight on while we're receiving
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if (!g_end_of_rx_detected_maybe && IS_NOT_NOAA_CHANNEL(g_rx_vfo->channel_save))
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{
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@ -404,11 +418,11 @@ Skip:
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{
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case SCAN_RESUME_TIME: // stay only for a limited time
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break;
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case SCAN_RESUME_CARRIER: // stay till the carrier goes away
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case SCAN_RESUME_CARRIER: // stay untill the carrier goes away
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g_scan_pause_10ms = g_eeprom.scan_hold_time_500ms * 50;
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g_scan_pause_time_mode = false;
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break;
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case SCAN_RESUME_SEARCH:
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case SCAN_RESUME_STOP: // stop scan once we find any signal
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APP_stop_scan();
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break;
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}
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@ -498,7 +512,7 @@ bool APP_start_listening(function_type_t Function, const bool reset_am_fix)
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g_scan_pause_10ms = g_eeprom.scan_hold_time_500ms * 50;
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g_scan_pause_time_mode = false;
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break;
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case SCAN_RESUME_SEARCH:
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case SCAN_RESUME_STOP:
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g_scan_pause_10ms = 0;
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g_scan_pause_time_mode = false;
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break;
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@ -549,14 +563,14 @@ bool APP_start_listening(function_type_t Function, const bool reset_am_fix)
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AM_fix_10ms(chan);
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}
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else
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BK4819_WriteRegister(BK4819_REG_13, (lna_short << 8) | (lna << 5) | (mixer << 3) | (pga << 0));
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BK4819_WriteRegister(0x13, (lna_short << 8) | (lna << 5) | (mixer << 3) | (pga << 0));
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}
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#else
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(void)reset_am_fix;
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#endif
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// AF gain - original QS values
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BK4819_WriteRegister(BK4819_REG_48,
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BK4819_WriteRegister(0x48,
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(11u << 12) | // ??? .. 0 to 15, doesn't seem to make any difference
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( 0u << 10) | // AF Rx Gain-1
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(g_eeprom.volume_gain << 4) | // AF Rx Gain-2
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@ -892,11 +906,11 @@ void APP_process_radio_interrupts(void)
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if (g_screen_to_display == DISPLAY_SEARCH)
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return;
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while (BK4819_ReadRegister(BK4819_REG_0C) & (1u << 0))
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while (BK4819_ReadRegister(0x0C) & (1u << 0))
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{ // BK chip interrupt request
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BK4819_WriteRegister(BK4819_REG_02, 0);
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const uint16_t interrupt_bits = BK4819_ReadRegister(BK4819_REG_02);
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BK4819_WriteRegister(0x02, 0);
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const uint16_t interrupt_bits = BK4819_ReadRegister(0x02);
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if (interrupt_bits & BK4819_REG_02_DTMF_5TONE_FOUND)
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{ // save the RX'ed DTMF character
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@ -384,9 +384,9 @@ static void cmd_0527(void)
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memset(&reply, 0, sizeof(reply));
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reply.Header.ID = 0x0528;
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reply.Header.Size = sizeof(reply.Data);
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reply.Data.RSSI = BK4819_ReadRegister(BK4819_REG_67) & 0x01FF;
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reply.Data.ExNoiseIndicator = BK4819_ReadRegister(BK4819_REG_65) & 0x007F;
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reply.Data.GlitchIndicator = BK4819_ReadRegister(BK4819_REG_63);
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reply.Data.RSSI = BK4819_ReadRegister(0x67) & 0x01FF;
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reply.Data.ExNoiseIndicator = BK4819_ReadRegister(0x65) & 0x007F;
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reply.Data.GlitchIndicator = BK4819_ReadRegister(0x63);
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SendReply(&reply, sizeof(reply));
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}
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4
audio.c
4
audio.c
@ -76,7 +76,7 @@ beep_type_t g_beep_to_play = BEEP_NONE;
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void AUDIO_PlayBeep(beep_type_t Beep)
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{
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const uint16_t ToneConfig = BK4819_ReadRegister(BK4819_REG_71);
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const uint16_t ToneConfig = BK4819_ReadRegister(0x71);
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uint16_t ToneFrequency;
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uint16_t Duration;
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@ -218,7 +218,7 @@ void AUDIO_PlayBeep(beep_type_t Beep)
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SYSTEM_DelayMs(2);
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// restore the register
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BK4819_WriteRegister(BK4819_REG_71, ToneConfig);
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BK4819_WriteRegister(0x71, ToneConfig);
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if (g_speaker_enabled)
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GPIO_SetBit(&GPIOC->DATA, GPIOC_PIN_SPEAKER);
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4
board.c
4
board.c
@ -841,8 +841,8 @@ void BOARD_EEPROM_LoadCalibration(void)
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g_eeprom.volume_gain = (Misc.volume_gain < 64) ? Misc.volume_gain : 58;
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g_eeprom.dac_gain = (Misc.dac_gain < 16) ? Misc.dac_gain : 8;
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BK4819_WriteRegister(BK4819_REG_3B, 22656 + g_eeprom.BK4819_xtal_freq_low);
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// BK4819_WriteRegister(BK4819_REG_3C, g_eeprom.BK4819_XTAL_FREQ_HIGH);
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BK4819_WriteRegister(0x3B, 22656 + g_eeprom.BK4819_xtal_freq_low);
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// BK4819_WriteRegister(0x3C, g_eeprom.BK4819_XTAL_FREQ_HIGH);
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}
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}
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@ -17,153 +17,77 @@
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#ifndef BK4819_REGS_H
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#define BK4819_REGS_H
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enum bk4819_register_e {
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BK4819_REG_00 = 0x00U,
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BK4819_REG_02 = 0x02U,
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BK4819_REG_06 = 0x06U,
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BK4819_REG_07 = 0x07U,
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BK4819_REG_08 = 0x08U,
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BK4819_REG_09 = 0x09U,
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BK4819_REG_0B = 0x0BU,
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BK4819_REG_0C = 0x0CU,
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BK4819_REG_0D = 0x0DU,
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BK4819_REG_0E = 0x0EU,
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BK4819_REG_10 = 0x10U,
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BK4819_REG_11 = 0x11U,
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BK4819_REG_12 = 0x12U,
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BK4819_REG_13 = 0x13U,
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BK4819_REG_14 = 0x14U,
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BK4819_REG_19 = 0x19U,
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BK4819_REG_1F = 0x1FU,
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BK4819_REG_20 = 0x20U,
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BK4819_REG_21 = 0x21U,
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BK4819_REG_24 = 0x24U,
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BK4819_REG_28 = 0x28U,
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BK4819_REG_29 = 0x29U,
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BK4819_REG_2B = 0x2BU,
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BK4819_REG_30 = 0x30U,
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BK4819_REG_31 = 0x31U,
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BK4819_REG_32 = 0x32U,
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BK4819_REG_33 = 0x33U,
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BK4819_REG_36 = 0x36U,
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BK4819_REG_37 = 0x37U,
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BK4819_REG_38 = 0x38U,
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BK4819_REG_39 = 0x39U,
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BK4819_REG_3A = 0x3AU,
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BK4819_REG_3B = 0x3BU,
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BK4819_REG_3C = 0x3CU,
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BK4819_REG_3E = 0x3EU,
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BK4819_REG_3F = 0x3FU,
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BK4819_REG_43 = 0x43U,
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BK4819_REG_46 = 0x46U,
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BK4819_REG_47 = 0x47U,
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BK4819_REG_48 = 0x48U,
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BK4819_REG_49 = 0x49U,
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BK4819_REG_4D = 0x4DU,
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BK4819_REG_4E = 0x4EU,
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BK4819_REG_4F = 0x4FU,
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BK4819_REG_50 = 0x50U,
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BK4819_REG_51 = 0x51U,
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BK4819_REG_52 = 0x52U,
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BK4819_REG_58 = 0x58U,
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BK4819_REG_59 = 0x59U,
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BK4819_REG_5A = 0x5AU,
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BK4819_REG_5B = 0x5BU,
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BK4819_REG_5C = 0x5CU,
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BK4819_REG_5D = 0x5DU,
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BK4819_REG_5F = 0x5FU,
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BK4819_REG_63 = 0x63U,
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BK4819_REG_64 = 0x64U,
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BK4819_REG_65 = 0x65U,
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BK4819_REG_67 = 0x67U,
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BK4819_REG_68 = 0x68U,
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BK4819_REG_69 = 0x69U,
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BK4819_REG_6A = 0x6AU,
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BK4819_REG_6F = 0x6FU,
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BK4819_REG_70 = 0x70U,
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BK4819_REG_71 = 0x71U,
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BK4819_REG_72 = 0x72U,
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BK4819_REG_78 = 0x78U,
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BK4819_REG_79 = 0x79U,
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BK4819_REG_7A = 0x7AU,
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BK4819_REG_7B = 0x7BU,
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BK4819_REG_7C = 0x7CU,
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BK4819_REG_7D = 0x7DU,
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BK4819_REG_7E = 0x7EU
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};
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typedef enum bk4819_register_e bk4819_register_t;
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enum bk4819_gpio_pin_e {
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BK4819_GPIO0_PIN28_RX_ENABLE = 0,
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BK4819_GPIO1_PIN29_PA_ENABLE = 1,
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BK4819_GPIO3_PIN31_UHF_LNA = 3,
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BK4819_GPIO4_PIN32_VHF_LNA = 4,
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BK4819_GPIO5_PIN1_RED = 5,
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BK4819_GPIO6_PIN2_GREEN = 6
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BK4819_GPIO0_PIN28_RX_ENABLE = 0,
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BK4819_GPIO1_PIN29_PA_ENABLE = 1,
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BK4819_GPIO3_PIN31_UHF_LNA = 3,
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BK4819_GPIO4_PIN32_VHF_LNA = 4,
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BK4819_GPIO5_PIN1_RED = 5,
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BK4819_GPIO6_PIN2_GREEN = 6
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};
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typedef enum bk4819_gpio_pin_e bk4819_gpio_pin_t;
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// REG 02
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#define BK4819_REG_02_SHIFT_FSK_TX_FINISHED 15
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#define BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY 14
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#define BK4819_REG_02_SHIFT_FSK_RX_FINISHED 13
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#define BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL 12
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#define BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND 11
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#define BK4819_REG_02_SHIFT_CxCSS_TAIL 10
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#define BK4819_REG_02_SHIFT_CDCSS_FOUND 9
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#define BK4819_REG_02_SHIFT_CDCSS_LOST 8
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#define BK4819_REG_02_SHIFT_CTCSS_FOUND 7
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#define BK4819_REG_02_SHIFT_CTCSS_LOST 6
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#define BK4819_REG_02_SHIFT_VOX_FOUND 5
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#define BK4819_REG_02_SHIFT_VOX_LOST 4
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#define BK4819_REG_02_SHIFT_SQUELCH_FOUND 3
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#define BK4819_REG_02_SHIFT_SQUELCH_LOST 2
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#define BK4819_REG_02_SHIFT_FSK_RX_SYNC 1
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#define BK4819_REG_02_SHIFT_FSK_TX_FINISHED 15
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#define BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY 14
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#define BK4819_REG_02_SHIFT_FSK_RX_FINISHED 13
|
||||
#define BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL 12
|
||||
#define BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND 11
|
||||
#define BK4819_REG_02_SHIFT_CxCSS_TAIL 10
|
||||
#define BK4819_REG_02_SHIFT_CDCSS_FOUND 9
|
||||
#define BK4819_REG_02_SHIFT_CDCSS_LOST 8
|
||||
#define BK4819_REG_02_SHIFT_CTCSS_FOUND 7
|
||||
#define BK4819_REG_02_SHIFT_CTCSS_LOST 6
|
||||
#define BK4819_REG_02_SHIFT_VOX_FOUND 5
|
||||
#define BK4819_REG_02_SHIFT_VOX_LOST 4
|
||||
#define BK4819_REG_02_SHIFT_SQUELCH_FOUND 3
|
||||
#define BK4819_REG_02_SHIFT_SQUELCH_LOST 2
|
||||
#define BK4819_REG_02_SHIFT_FSK_RX_SYNC 1
|
||||
|
||||
#define BK4819_REG_02_MASK_FSK_TX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_TX)
|
||||
#define BK4819_REG_02_MASK_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY)
|
||||
#define BK4819_REG_02_MASK_FSK_RX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_RX_FINISHED)
|
||||
#define BK4819_REG_02_MASK_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL)
|
||||
#define BK4819_REG_02_MASK_DTMF_5TONE_FOUND (1U << BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND)
|
||||
#define BK4819_REG_02_MASK_CxCSS_TAIL (1U << BK4819_REG_02_SHIFT_CxCSS_TAIL)
|
||||
#define BK4819_REG_02_MASK_CDCSS_FOUND (1U << BK4819_REG_02_SHIFT_CDCSS_FOUND)
|
||||
#define BK4819_REG_02_MASK_CDCSS_LOST (1U << BK4819_REG_02_SHIFT_CDCSS_LOST)
|
||||
#define BK4819_REG_02_MASK_CTCSS_FOUND (1U << BK4819_REG_02_SHIFT_CTCSS_FOUND)
|
||||
#define BK4819_REG_02_MASK_CTCSS_LOST (1U << BK4819_REG_02_SHIFT_CTCSS_LOST)
|
||||
#define BK4819_REG_02_MASK_VOX_FOUND (1U << BK4819_REG_02_SHIFT_VOX_FOUND)
|
||||
#define BK4819_REG_02_MASK_VOX_LOST (1U << BK4819_REG_02_SHIFT_VOX_LOST)
|
||||
#define BK4819_REG_02_MASK_SQUELCH_FOUND (1U << BK4819_REG_02_SHIFT_SQUELCH_FOUND)
|
||||
#define BK4819_REG_02_MASK_SQUELCH_LOST (1U << BK4819_REG_02_SHIFT_SQUELCH_LOST)
|
||||
#define BK4819_REG_02_MASK_FSK_RX_SYNC (1U << BK4819_REG_02_SHIFT_FSK_RX_SYNC)
|
||||
#define BK4819_REG_02_MASK_FSK_TX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_TX)
|
||||
#define BK4819_REG_02_MASK_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY)
|
||||
#define BK4819_REG_02_MASK_FSK_RX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_RX_FINISHED)
|
||||
#define BK4819_REG_02_MASK_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL)
|
||||
#define BK4819_REG_02_MASK_DTMF_5TONE_FOUND (1U << BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND)
|
||||
#define BK4819_REG_02_MASK_CxCSS_TAIL (1U << BK4819_REG_02_SHIFT_CxCSS_TAIL)
|
||||
#define BK4819_REG_02_MASK_CDCSS_FOUND (1U << BK4819_REG_02_SHIFT_CDCSS_FOUND)
|
||||
#define BK4819_REG_02_MASK_CDCSS_LOST (1U << BK4819_REG_02_SHIFT_CDCSS_LOST)
|
||||
#define BK4819_REG_02_MASK_CTCSS_FOUND (1U << BK4819_REG_02_SHIFT_CTCSS_FOUND)
|
||||
#define BK4819_REG_02_MASK_CTCSS_LOST (1U << BK4819_REG_02_SHIFT_CTCSS_LOST)
|
||||
#define BK4819_REG_02_MASK_VOX_FOUND (1U << BK4819_REG_02_SHIFT_VOX_FOUND)
|
||||
#define BK4819_REG_02_MASK_VOX_LOST (1U << BK4819_REG_02_SHIFT_VOX_LOST)
|
||||
#define BK4819_REG_02_MASK_SQUELCH_FOUND (1U << BK4819_REG_02_SHIFT_SQUELCH_FOUND)
|
||||
#define BK4819_REG_02_MASK_SQUELCH_LOST (1U << BK4819_REG_02_SHIFT_SQUELCH_LOST)
|
||||
#define BK4819_REG_02_MASK_FSK_RX_SYNC (1U << BK4819_REG_02_SHIFT_FSK_RX_SYNC)
|
||||
|
||||
#define BK4819_REG_02_FSK_TX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_TX_FINISHED)
|
||||
#define BK4819_REG_02_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY)
|
||||
#define BK4819_REG_02_FSK_RX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_RX_FINISHED)
|
||||
#define BK4819_REG_02_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL)
|
||||
#define BK4819_REG_02_DTMF_5TONE_FOUND (1U << BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND)
|
||||
#define BK4819_REG_02_CxCSS_TAIL (1U << BK4819_REG_02_SHIFT_CxCSS_TAIL)
|
||||
#define BK4819_REG_02_CDCSS_FOUND (1U << BK4819_REG_02_SHIFT_CDCSS_FOUND)
|
||||
#define BK4819_REG_02_CDCSS_LOST (1U << BK4819_REG_02_SHIFT_CDCSS_LOST)
|
||||
#define BK4819_REG_02_CTCSS_FOUND (1U << BK4819_REG_02_SHIFT_CTCSS_FOUND)
|
||||
#define BK4819_REG_02_CTCSS_LOST (1U << BK4819_REG_02_SHIFT_CTCSS_LOST)
|
||||
#define BK4819_REG_02_VOX_FOUND (1U << BK4819_REG_02_SHIFT_VOX_FOUND)
|
||||
#define BK4819_REG_02_VOX_LOST (1U << BK4819_REG_02_SHIFT_VOX_LOST)
|
||||
#define BK4819_REG_02_SQUELCH_CLOSED (1U << BK4819_REG_02_SHIFT_SQUELCH_FOUND)
|
||||
#define BK4819_REG_02_SQUELCH_OPENED (1U << BK4819_REG_02_SHIFT_SQUELCH_LOST)
|
||||
#define BK4819_REG_02_FSK_RX_SYNC (1U << BK4819_REG_02_SHIFT_FSK_RX_SYNC)
|
||||
#define BK4819_REG_02_FSK_TX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_TX_FINISHED)
|
||||
#define BK4819_REG_02_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_EMPTY)
|
||||
#define BK4819_REG_02_FSK_RX_FINISHED (1U << BK4819_REG_02_SHIFT_FSK_RX_FINISHED)
|
||||
#define BK4819_REG_02_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_02_SHIFT_FSK_FIFO_ALMOST_FULL)
|
||||
#define BK4819_REG_02_DTMF_5TONE_FOUND (1U << BK4819_REG_02_SHIFT_DTMF_5TONE_FOUND)
|
||||
#define BK4819_REG_02_CxCSS_TAIL (1U << BK4819_REG_02_SHIFT_CxCSS_TAIL)
|
||||
#define BK4819_REG_02_CDCSS_FOUND (1U << BK4819_REG_02_SHIFT_CDCSS_FOUND)
|
||||
#define BK4819_REG_02_CDCSS_LOST (1U << BK4819_REG_02_SHIFT_CDCSS_LOST)
|
||||
#define BK4819_REG_02_CTCSS_FOUND (1U << BK4819_REG_02_SHIFT_CTCSS_FOUND)
|
||||
#define BK4819_REG_02_CTCSS_LOST (1U << BK4819_REG_02_SHIFT_CTCSS_LOST)
|
||||
#define BK4819_REG_02_VOX_FOUND (1U << BK4819_REG_02_SHIFT_VOX_FOUND)
|
||||
#define BK4819_REG_02_VOX_LOST (1U << BK4819_REG_02_SHIFT_VOX_LOST)
|
||||
#define BK4819_REG_02_SQUELCH_CLOSED (1U << BK4819_REG_02_SHIFT_SQUELCH_FOUND)
|
||||
#define BK4819_REG_02_SQUELCH_OPENED (1U << BK4819_REG_02_SHIFT_SQUELCH_LOST)
|
||||
#define BK4819_REG_02_FSK_RX_SYNC (1U << BK4819_REG_02_SHIFT_FSK_RX_SYNC)
|
||||
|
||||
// REG 07
|
||||
|
||||
#define BK4819_REG_07_SHIFT_FREQUENCY_MODE 13
|
||||
#define BK4819_REG_07_SHIFT_FREQUENCY 0
|
||||
#define BK4819_REG_07_SHIFT_FREQUENCY_MODE 13
|
||||
#define BK4819_REG_07_SHIFT_FREQUENCY 0
|
||||
|
||||
#define BK4819_REG_07_MASK_FREQUENCY_MODE (0x0007U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
|
||||
#define BK4819_REG_07_MASK_FREQUENCY (0x1FFFU << BK4819_REG_07_SHIFT_FREQUENCY)
|
||||
#define BK4819_REG_07_MASK_FREQUENCY_MODE (0x0007U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
|
||||
#define BK4819_REG_07_MASK_FREQUENCY (0x1FFFU << BK4819_REG_07_SHIFT_FREQUENCY)
|
||||
|
||||
#define BK4819_REG_07_MODE_CTC1 (0U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
|
||||
#define BK4819_REG_07_MODE_CTC2 (1U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
|
||||
#define BK4819_REG_07_MODE_CDCSS (2U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
|
||||
#define BK4819_REG_07_MODE_CTC1 (0U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
|
||||
#define BK4819_REG_07_MODE_CTC2 (1U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
|
||||
#define BK4819_REG_07_MODE_CDCSS (2U << BK4819_REG_07_SHIFT_FREQUENCY_MODE)
|
||||
|
||||
// REG 24
|
||||
|
||||
@ -186,100 +110,100 @@ typedef enum bk4819_gpio_pin_e bk4819_gpio_pin_t;
|
||||
|
||||
// REG 30
|
||||
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB 15
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_UNKNOWN 14
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_RX_LINK 10
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_AF_DAC 9
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_DISC_MODE 8
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_PLL_VCO 4
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_PA_GAIN 3
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_MIC_ADC 2
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_TX_DSP 1
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_RX_DSP 0
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB 15
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_UNKNOWN 14
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_RX_LINK 10
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_AF_DAC 9
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_DISC_MODE 8
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_PLL_VCO 4
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_PA_GAIN 3
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_MIC_ADC 2
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_TX_DSP 1
|
||||
#define BK4819_REG_30_SHIFT_ENABLE_RX_DSP 0
|
||||
|
||||
#define BK4819_REG_30_MASK_ENABLE_VCO_CALIB (0x1U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB)
|
||||
#define BK4819_REG_30_MASK_ENABLE_UNKNOWN (0x1U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN)
|
||||
#define BK4819_REG_30_MASK_ENABLE_RX_LINK (0xFU << BK4819_REG_30_SHIFT_ENABLE_RX_LINK)
|
||||
#define BK4819_REG_30_MASK_ENABLE_AF_DAC (0x1U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC)
|
||||
#define BK4819_REG_30_MASK_ENABLE_DISC_MODE (0x1U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE)
|
||||
#define BK4819_REG_30_MASK_ENABLE_PLL_VCO (0xFU << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO)
|
||||
#define BK4819_REG_30_MASK_ENABLE_PA_GAIN (0x1U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN)
|
||||
#define BK4819_REG_30_MASK_ENABLE_MIC_ADC (0x1U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC)
|
||||
#define BK4819_REG_30_MASK_ENABLE_TX_DSP (0x1U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP)
|
||||
#define BK4819_REG_30_MASK_ENABLE_RX_DSP (0x1U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP)
|
||||
#define BK4819_REG_30_MASK_ENABLE_VCO_CALIB (0x1U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB)
|
||||
#define BK4819_REG_30_MASK_ENABLE_UNKNOWN (0x1U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN)
|
||||
#define BK4819_REG_30_MASK_ENABLE_RX_LINK (0xFU << BK4819_REG_30_SHIFT_ENABLE_RX_LINK)
|
||||
#define BK4819_REG_30_MASK_ENABLE_AF_DAC (0x1U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC)
|
||||
#define BK4819_REG_30_MASK_ENABLE_DISC_MODE (0x1U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE)
|
||||
#define BK4819_REG_30_MASK_ENABLE_PLL_VCO (0xFU << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO)
|
||||
#define BK4819_REG_30_MASK_ENABLE_PA_GAIN (0x1U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN)
|
||||
#define BK4819_REG_30_MASK_ENABLE_MIC_ADC (0x1U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC)
|
||||
#define BK4819_REG_30_MASK_ENABLE_TX_DSP (0x1U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP)
|
||||
#define BK4819_REG_30_MASK_ENABLE_RX_DSP (0x1U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP)
|
||||
|
||||
enum {
|
||||
BK4819_REG_30_ENABLE_VCO_CALIB = (0x1U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB),
|
||||
BK4819_REG_30_DISABLE_VCO_CALIB = (0x0U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB),
|
||||
BK4819_REG_30_ENABLE_UNKNOWN = (0x1U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN),
|
||||
BK4819_REG_30_DISABLE_UNKNOWN = (0x0U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN),
|
||||
BK4819_REG_30_ENABLE_RX_LINK = (0xFU << BK4819_REG_30_SHIFT_ENABLE_RX_LINK),
|
||||
BK4819_REG_30_DISABLE_RX_LINK = (0x0U << BK4819_REG_30_SHIFT_ENABLE_RX_LINK),
|
||||
BK4819_REG_30_ENABLE_AF_DAC = (0x1U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC),
|
||||
BK4819_REG_30_DISABLE_AF_DAC = (0x0U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC),
|
||||
BK4819_REG_30_ENABLE_DISC_MODE = (0x1U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE),
|
||||
BK4819_REG_30_DISABLE_DISC_MODE = (0x0U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE),
|
||||
BK4819_REG_30_ENABLE_PLL_VCO = (0xFU << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO),
|
||||
BK4819_REG_30_DISABLE_PLL_VCO = (0x0U << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO),
|
||||
BK4819_REG_30_ENABLE_PA_GAIN = (0x1U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN),
|
||||
BK4819_REG_30_DISABLE_PA_GAIN = (0x0U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN),
|
||||
BK4819_REG_30_ENABLE_MIC_ADC = (0x1U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC),
|
||||
BK4819_REG_30_DISABLE_MIC_ADC = (0x0U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC),
|
||||
BK4819_REG_30_ENABLE_TX_DSP = (0x1U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP),
|
||||
BK4819_REG_30_DISABLE_TX_DSP = (0x0U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP),
|
||||
BK4819_REG_30_ENABLE_RX_DSP = (0x1U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP),
|
||||
BK4819_REG_30_DISABLE_RX_DSP = (0x0U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP),
|
||||
BK4819_REG_30_ENABLE_VCO_CALIB = (0x1U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB),
|
||||
BK4819_REG_30_DISABLE_VCO_CALIB = (0x0U << BK4819_REG_30_SHIFT_ENABLE_VCO_CALIB),
|
||||
BK4819_REG_30_ENABLE_UNKNOWN = (0x1U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN),
|
||||
BK4819_REG_30_DISABLE_UNKNOWN = (0x0U << BK4819_REG_30_SHIFT_ENABLE_UNKNOWN),
|
||||
BK4819_REG_30_ENABLE_RX_LINK = (0xFU << BK4819_REG_30_SHIFT_ENABLE_RX_LINK),
|
||||
BK4819_REG_30_DISABLE_RX_LINK = (0x0U << BK4819_REG_30_SHIFT_ENABLE_RX_LINK),
|
||||
BK4819_REG_30_ENABLE_AF_DAC = (0x1U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC),
|
||||
BK4819_REG_30_DISABLE_AF_DAC = (0x0U << BK4819_REG_30_SHIFT_ENABLE_AF_DAC),
|
||||
BK4819_REG_30_ENABLE_DISC_MODE = (0x1U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE),
|
||||
BK4819_REG_30_DISABLE_DISC_MODE = (0x0U << BK4819_REG_30_SHIFT_ENABLE_DISC_MODE),
|
||||
BK4819_REG_30_ENABLE_PLL_VCO = (0xFU << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO),
|
||||
BK4819_REG_30_DISABLE_PLL_VCO = (0x0U << BK4819_REG_30_SHIFT_ENABLE_PLL_VCO),
|
||||
BK4819_REG_30_ENABLE_PA_GAIN = (0x1U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN),
|
||||
BK4819_REG_30_DISABLE_PA_GAIN = (0x0U << BK4819_REG_30_SHIFT_ENABLE_PA_GAIN),
|
||||
BK4819_REG_30_ENABLE_MIC_ADC = (0x1U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC),
|
||||
BK4819_REG_30_DISABLE_MIC_ADC = (0x0U << BK4819_REG_30_SHIFT_ENABLE_MIC_ADC),
|
||||
BK4819_REG_30_ENABLE_TX_DSP = (0x1U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP),
|
||||
BK4819_REG_30_DISABLE_TX_DSP = (0x0U << BK4819_REG_30_SHIFT_ENABLE_TX_DSP),
|
||||
BK4819_REG_30_ENABLE_RX_DSP = (0x1U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP),
|
||||
BK4819_REG_30_DISABLE_RX_DSP = (0x0U << BK4819_REG_30_SHIFT_ENABLE_RX_DSP),
|
||||
};
|
||||
|
||||
// REG 3F
|
||||
|
||||
#define BK4819_REG_3F_SHIFT_FSK_TX_FINISHED 15
|
||||
#define BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY 14
|
||||
#define BK4819_REG_3F_SHIFT_FSK_RX_FINISHED 13
|
||||
#define BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL 12
|
||||
#define BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND 11
|
||||
#define BK4819_REG_3F_SHIFT_CxCSS_TAIL 10
|
||||
#define BK4819_REG_3F_SHIFT_CDCSS_FOUND 9
|
||||
#define BK4819_REG_3F_SHIFT_CDCSS_LOST 8
|
||||
#define BK4819_REG_3F_SHIFT_CTCSS_FOUND 7
|
||||
#define BK4819_REG_3F_SHIFT_CTCSS_LOST 6
|
||||
#define BK4819_REG_3F_SHIFT_VOX_FOUND 5
|
||||
#define BK4819_REG_3F_SHIFT_VOX_LOST 4
|
||||
#define BK4819_REG_3F_SHIFT_SQUELCH_FOUND 3
|
||||
#define BK4819_REG_3F_SHIFT_SQUELCH_LOST 2
|
||||
#define BK4819_REG_3F_SHIFT_FSK_RX_SYNC 1
|
||||
#define BK4819_REG_3F_SHIFT_FSK_TX_FINISHED 15
|
||||
#define BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY 14
|
||||
#define BK4819_REG_3F_SHIFT_FSK_RX_FINISHED 13
|
||||
#define BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL 12
|
||||
#define BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND 11
|
||||
#define BK4819_REG_3F_SHIFT_CxCSS_TAIL 10
|
||||
#define BK4819_REG_3F_SHIFT_CDCSS_FOUND 9
|
||||
#define BK4819_REG_3F_SHIFT_CDCSS_LOST 8
|
||||
#define BK4819_REG_3F_SHIFT_CTCSS_FOUND 7
|
||||
#define BK4819_REG_3F_SHIFT_CTCSS_LOST 6
|
||||
#define BK4819_REG_3F_SHIFT_VOX_FOUND 5
|
||||
#define BK4819_REG_3F_SHIFT_VOX_LOST 4
|
||||
#define BK4819_REG_3F_SHIFT_SQUELCH_FOUND 3
|
||||
#define BK4819_REG_3F_SHIFT_SQUELCH_LOST 2
|
||||
#define BK4819_REG_3F_SHIFT_FSK_RX_SYNC 1
|
||||
|
||||
#define BK4819_REG_3F_MASK_FSK_TX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_TX)
|
||||
#define BK4819_REG_3F_MASK_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY)
|
||||
#define BK4819_REG_3F_MASK_FSK_RX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_RX_FINISHED)
|
||||
#define BK4819_REG_3F_MASK_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL)
|
||||
#define BK4819_REG_3F_MASK_DTMF_5TONE_FOUND (1U << BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND)
|
||||
#define BK4819_REG_3F_MASK_CxCSS_TAIL (1U << BK4819_REG_3F_SHIFT_CxCSS_TAIL)
|
||||
#define BK4819_REG_3F_MASK_CDCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CDCSS_FOUND)
|
||||
#define BK4819_REG_3F_MASK_CDCSS_LOST (1U << BK4819_REG_3F_SHIFT_CDCSS_LOST)
|
||||
#define BK4819_REG_3F_MASK_CTCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CTCSS_FOUND)
|
||||
#define BK4819_REG_3F_MASK_CTCSS_LOST (1U << BK4819_REG_3F_SHIFT_CTCSS_LOST)
|
||||
#define BK4819_REG_3F_MASK_VOX_FOUND (1U << BK4819_REG_3F_SHIFT_VOX_FOUND)
|
||||
#define BK4819_REG_3F_MASK_VOX_LOST (1U << BK4819_REG_3F_SHIFT_VOX_LOST)
|
||||
#define BK4819_REG_3F_MASK_SQUELCH_FOUND (1U << BK4819_REG_3F_SHIFT_SQUELCH_FOUND)
|
||||
#define BK4819_REG_3F_MASK_SQUELCH_LOST (1U << BK4819_REG_3F_SHIFT_SQUELCH_LOST)
|
||||
#define BK4819_REG_3F_MASK_FSK_RX_SYNC (1U << BK4819_REG_3F_SHIFT_FSK_RX_SYNC)
|
||||
#define BK4819_REG_3F_MASK_FSK_TX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_TX)
|
||||
#define BK4819_REG_3F_MASK_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY)
|
||||
#define BK4819_REG_3F_MASK_FSK_RX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_RX_FINISHED)
|
||||
#define BK4819_REG_3F_MASK_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL)
|
||||
#define BK4819_REG_3F_MASK_DTMF_5TONE_FOUND (1U << BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND)
|
||||
#define BK4819_REG_3F_MASK_CxCSS_TAIL (1U << BK4819_REG_3F_SHIFT_CxCSS_TAIL)
|
||||
#define BK4819_REG_3F_MASK_CDCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CDCSS_FOUND)
|
||||
#define BK4819_REG_3F_MASK_CDCSS_LOST (1U << BK4819_REG_3F_SHIFT_CDCSS_LOST)
|
||||
#define BK4819_REG_3F_MASK_CTCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CTCSS_FOUND)
|
||||
#define BK4819_REG_3F_MASK_CTCSS_LOST (1U << BK4819_REG_3F_SHIFT_CTCSS_LOST)
|
||||
#define BK4819_REG_3F_MASK_VOX_FOUND (1U << BK4819_REG_3F_SHIFT_VOX_FOUND)
|
||||
#define BK4819_REG_3F_MASK_VOX_LOST (1U << BK4819_REG_3F_SHIFT_VOX_LOST)
|
||||
#define BK4819_REG_3F_MASK_SQUELCH_FOUND (1U << BK4819_REG_3F_SHIFT_SQUELCH_FOUND)
|
||||
#define BK4819_REG_3F_MASK_SQUELCH_LOST (1U << BK4819_REG_3F_SHIFT_SQUELCH_LOST)
|
||||
#define BK4819_REG_3F_MASK_FSK_RX_SYNC (1U << BK4819_REG_3F_SHIFT_FSK_RX_SYNC)
|
||||
|
||||
#define BK4819_REG_3F_FSK_TX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_TX_FINISHED)
|
||||
#define BK4819_REG_3F_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY)
|
||||
#define BK4819_REG_3F_FSK_RX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_RX_FINISHED)
|
||||
#define BK4819_REG_3F_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL)
|
||||
#define BK4819_REG_3F_DTMF_5TONE_FOUND (1U << BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND)
|
||||
#define BK4819_REG_3F_CxCSS_TAIL (1U << BK4819_REG_3F_SHIFT_CxCSS_TAIL)
|
||||
#define BK4819_REG_3F_CDCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CDCSS_FOUND)
|
||||
#define BK4819_REG_3F_CDCSS_LOST (1U << BK4819_REG_3F_SHIFT_CDCSS_LOST)
|
||||
#define BK4819_REG_3F_CTCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CTCSS_FOUND)
|
||||
#define BK4819_REG_3F_CTCSS_LOST (1U << BK4819_REG_3F_SHIFT_CTCSS_LOST)
|
||||
#define BK4819_REG_3F_VOX_FOUND (1U << BK4819_REG_3F_SHIFT_VOX_FOUND)
|
||||
#define BK4819_REG_3F_VOX_LOST (1U << BK4819_REG_3F_SHIFT_VOX_LOST)
|
||||
#define BK4819_REG_3F_SQUELCH_FOUND (1U << BK4819_REG_3F_SHIFT_SQUELCH_FOUND)
|
||||
#define BK4819_REG_3F_SQUELCH_LOST (1U << BK4819_REG_3F_SHIFT_SQUELCH_LOST)
|
||||
#define BK4819_REG_3F_FSK_RX_SYNC (1U << BK4819_REG_3F_SHIFT_FSK_RX_SYNC)
|
||||
#define BK4819_REG_3F_FSK_TX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_TX_FINISHED)
|
||||
#define BK4819_REG_3F_FSK_FIFO_ALMOST_EMPTY (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_EMPTY)
|
||||
#define BK4819_REG_3F_FSK_RX_FINISHED (1U << BK4819_REG_3F_SHIFT_FSK_RX_FINISHED)
|
||||
#define BK4819_REG_3F_FSK_FIFO_ALMOST_FULL (1U << BK4819_REG_3F_SHIFT_FSK_FIFO_ALMOST_FULL)
|
||||
#define BK4819_REG_3F_DTMF_5TONE_FOUND (1U << BK4819_REG_3F_SHIFT_DTMF_5TONE_FOUND)
|
||||
#define BK4819_REG_3F_CxCSS_TAIL (1U << BK4819_REG_3F_SHIFT_CxCSS_TAIL)
|
||||
#define BK4819_REG_3F_CDCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CDCSS_FOUND)
|
||||
#define BK4819_REG_3F_CDCSS_LOST (1U << BK4819_REG_3F_SHIFT_CDCSS_LOST)
|
||||
#define BK4819_REG_3F_CTCSS_FOUND (1U << BK4819_REG_3F_SHIFT_CTCSS_FOUND)
|
||||
#define BK4819_REG_3F_CTCSS_LOST (1U << BK4819_REG_3F_SHIFT_CTCSS_LOST)
|
||||
#define BK4819_REG_3F_VOX_FOUND (1U << BK4819_REG_3F_SHIFT_VOX_FOUND)
|
||||
#define BK4819_REG_3F_VOX_LOST (1U << BK4819_REG_3F_SHIFT_VOX_LOST)
|
||||
#define BK4819_REG_3F_SQUELCH_FOUND (1U << BK4819_REG_3F_SHIFT_SQUELCH_FOUND)
|
||||
#define BK4819_REG_3F_SQUELCH_LOST (1U << BK4819_REG_3F_SHIFT_SQUELCH_LOST)
|
||||
#define BK4819_REG_3F_FSK_RX_SYNC (1U << BK4819_REG_3F_SHIFT_FSK_RX_SYNC)
|
||||
|
||||
// REG 51
|
||||
|
||||
@ -345,8 +269,8 @@ enum {
|
||||
#define BK4819_REG_70_MASK_TONE2_TUNING_GAIN (0x7Fu << BK4819_REG_70_SHIFT_TONE2_TUNING_GAIN)
|
||||
|
||||
enum {
|
||||
BK4819_REG_70_ENABLE_TONE1 = (1u << BK4819_REG_70_SHIFT_ENABLE_TONE1),
|
||||
BK4819_REG_70_ENABLE_TONE2 = (1u << BK4819_REG_70_SHIFT_ENABLE_TONE2)
|
||||
BK4819_REG_70_ENABLE_TONE1 = (1u << BK4819_REG_70_SHIFT_ENABLE_TONE1),
|
||||
BK4819_REG_70_ENABLE_TONE2 = (1u << BK4819_REG_70_SHIFT_ENABLE_TONE2)
|
||||
};
|
||||
|
||||
// *****************
|
||||
|
||||
394
driver/bk4819.c
394
driver/bk4819.c
File diff suppressed because it is too large
Load Diff
@ -62,8 +62,8 @@ typedef enum BK4819_CSS_scan_result_e BK4819_CSS_scan_result_t;
|
||||
extern bool g_rx_idle_mode;
|
||||
|
||||
void BK4819_Init(void);
|
||||
uint16_t BK4819_ReadRegister(bk4819_register_t Register);
|
||||
void BK4819_WriteRegister(bk4819_register_t Register, uint16_t Data);
|
||||
uint16_t BK4819_ReadRegister(const uint8_t Register);
|
||||
void BK4819_WriteRegister(const uint8_t Register, uint16_t Data);
|
||||
void BK4819_WriteU8(uint8_t Data);
|
||||
void BK4819_WriteU16(uint16_t Data);
|
||||
|
||||
|
||||
BIN
firmware.bin
BIN
firmware.bin
Binary file not shown.
Binary file not shown.
12
radio.c
12
radio.c
@ -624,17 +624,17 @@ void RADIO_setup_registers(bool switch_to_function_foreground)
|
||||
|
||||
while (1)
|
||||
{ // wait for the interrupt to clear ?
|
||||
const uint16_t status_bits = BK4819_ReadRegister(BK4819_REG_0C);
|
||||
const uint16_t status_bits = BK4819_ReadRegister(0x0C);
|
||||
if ((status_bits & (1u << 0)) == 0)
|
||||
break;
|
||||
BK4819_WriteRegister(BK4819_REG_02, 0); // clear the interrupt bits
|
||||
BK4819_WriteRegister(0x02, 0); // clear the interrupt bits
|
||||
SYSTEM_DelayMs(1);
|
||||
}
|
||||
|
||||
BK4819_WriteRegister(BK4819_REG_3F, 0); // disable interrupts
|
||||
BK4819_WriteRegister(0x3F, 0); // disable interrupts
|
||||
|
||||
// mic gain 0.5dB/step 0 to 31
|
||||
BK4819_WriteRegister(BK4819_REG_7D, 0xE940 | (g_eeprom.mic_sensitivity_tuning & 0x1f));
|
||||
BK4819_WriteRegister(0x7D, 0xE940 | (g_eeprom.mic_sensitivity_tuning & 0x1f));
|
||||
|
||||
#ifdef ENABLE_NOAA
|
||||
if (IS_NOAA_CHANNEL(g_rx_vfo->channel_save) && g_is_noaa_mode)
|
||||
@ -654,7 +654,7 @@ void RADIO_setup_registers(bool switch_to_function_foreground)
|
||||
BK4819_set_GPIO_pin(BK4819_GPIO0_PIN28_RX_ENABLE, true);
|
||||
|
||||
// AF RX Gain and DAC
|
||||
BK4819_WriteRegister(BK4819_REG_48, 0xB3A8); // 1011 00 111010 1000
|
||||
BK4819_WriteRegister(0x48, 0xB3A8); // 1011 00 111010 1000
|
||||
|
||||
interrupt_mask = BK4819_REG_3F_SQUELCH_FOUND | BK4819_REG_3F_SQUELCH_LOST;
|
||||
|
||||
@ -781,7 +781,7 @@ void RADIO_setup_registers(bool switch_to_function_foreground)
|
||||
#endif
|
||||
|
||||
// enable/disable BK4819 selected interrupts
|
||||
BK4819_WriteRegister(BK4819_REG_3F, interrupt_mask);
|
||||
BK4819_WriteRegister(0x3F, interrupt_mask);
|
||||
|
||||
FUNCTION_Init();
|
||||
|
||||
|
||||
@ -48,7 +48,7 @@ enum {
|
||||
enum {
|
||||
SCAN_RESUME_TIME = 0,
|
||||
SCAN_RESUME_CARRIER,
|
||||
SCAN_RESUME_SEARCH
|
||||
SCAN_RESUME_STOP
|
||||
};
|
||||
|
||||
enum {
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user