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OneOfEleven 2023-11-10 13:36:02 +00:00
parent ef5270e115
commit 630c6ac196
9 changed files with 18 additions and 16 deletions
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2
Makefile
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@ -258,6 +258,8 @@ endif
CFLAGS =
CFLAGS += -DCPU_CLOCK_HZ=48000000
ifeq ($(ENABLE_CLANG),0)
#CFLAGS += -Os -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c11 -MMD
CFLAGS += -Os -Werror -mcpu=cortex-m0 -freorder-blocks-algorithm=stc -std=c11 -MMD

4
board.c
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@ -51,8 +51,8 @@
FLASH_ConfigureTrimValues();
SYSTEM_ConfigureClocks();
overlay_FLASH_MainClock = 48000000;
overlay_FLASH_ClockMultiplier = 48;
overlay_FLASH_MainClock = CPU_CLOCK_HZ;
overlay_FLASH_ClockMultiplier = CPU_CLOCK_HZ / 1000000;
FLASH_Init(FLASH_READ_MODE_2_CYCLE);
}

2
driver/backlight.c
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@ -28,7 +28,7 @@ void BACKLIGHT_init(void)
{
// 48MHz / 94 / 1024 ~ 500Hz
const uint32_t PWM_FREQUENCY_HZ = 1000;
PWM_PLUS0_CLKSRC |= ((48000000 / 1024 / PWM_FREQUENCY_HZ) << 16);
PWM_PLUS0_CLKSRC |= ((CPU_CLOCK_HZ / 1024 / PWM_FREQUENCY_HZ) << 16);
PWM_PLUS0_PERIOD = 1023;
PORTCON_PORTB_SEL0 &= ~(PORTCON_PORTB_SEL0_B6_MASK);

12
driver/uart.c
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@ -31,17 +31,17 @@ void UART_Init(void)
uint32_t Frequency;
UART1->CTRL = (UART1->CTRL & ~UART_CTRL_UARTEN_MASK) | UART_CTRL_UARTEN_BITS_DISABLE;
Delta = SYSCON_RC_FREQ_DELTA;
Positive = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT;
Frequency = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT;
Frequency = Positive ? Frequency + 48000000U : 48000000U - Frequency;
Delta = SYSCON_RC_FREQ_DELTA;
Positive = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_SIG_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_SIG_SHIFT;
Frequency = (Delta & SYSCON_RC_FREQ_DELTA_RCHF_DELTA_MASK) >> SYSCON_RC_FREQ_DELTA_RCHF_DELTA_SHIFT;
Frequency = Positive ? Frequency + CPU_CLOCK_HZ : CPU_CLOCK_HZ - Frequency;
UART1->BAUD = Frequency / 39053U;
UART1->CTRL = UART_CTRL_RXEN_BITS_ENABLE | UART_CTRL_TXEN_BITS_ENABLE | UART_CTRL_RXDMAEN_BITS_ENABLE;
UART1->RXTO = 4;
UART1->FC = 0;
UART1->FC = 0;
UART1->FIFO = UART_FIFO_RF_LEVEL_BITS_8_BYTE | UART_FIFO_RF_CLR_BITS_ENABLE | UART_FIFO_TF_CLR_BITS_ENABLE;
UART1->IE = 0;
UART1->IE = 0;
DMA_CTR = (DMA_CTR & ~DMA_CTR_DMAEN_MASK) | DMA_CTR_DMAEN_BITS_DISABLE;

10
external/CMSIS_5/CMSIS/DAP/Firmware/Examples/MCU-LINK/fsl_usart.c vendored
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@ -5,7 +5,7 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/*
* Modified by Arm
*/
@ -334,7 +334,7 @@ void USART_GetDefaultConfig(usart_config_t *config)
/*!
* brief Sets the USART instance baud rate.
*
* This function configures the USART module baud rate.
* This function configures the USART module baud rate.
*
* USART_SetBaudRate(USART1, 115200U, 20000000U);
* endcode
@ -363,12 +363,12 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src
flexcomm_idx = FLEXCOMM_GetInstance(base);
flexcomm_clock = CLOCK_GetFlexCommInputClock(flexcomm_idx);
if (flexcomm_clock != 48000000U)
if (flexcomm_clock != CPU_CLOCK_HZ)
{
/* FlexComm input clock must be 48000000 */
return kStatus_USART_BaudrateNotSupport;
}
/* Calculate fixed point divider (12 LSBs are fractional part) */
div = (uint32_t)(((uint64_t)flexcomm_clock << FRACT_BITS) / (uint64_t)baudrate_Bps);
@ -376,7 +376,7 @@ status_t USART_SetBaudRate(USART_Type *base, uint32_t baudrate_Bps, uint32_t src
{
return kStatus_USART_BaudrateNotSupport;
}
br_div_best = 0U;
if ((div & ((1 << FRACT_BITS) - 1U)) == 0U)
{

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firmware.bin
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firmware.packed.bin
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3
sram-overlay.c
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@ -23,7 +23,7 @@
static volatile uint32_t *pFlash = 0;
uint32_t overlay_FLASH_MainClock;
uint32_t overlay_FLASH_ClockMultiplier;
uint32_t overlay_0x20000478; // Nothing is using this???
//uint32_t overlay_0x20000478; // Nothing is using this???
void overlay_FLASH_RebootToBootloader(void)
{
@ -86,7 +86,6 @@ void overlay_FLASH_Unlock(void)
uint32_t overlay_FLASH_ReadByAHB(uint32_t Offset)
{
return pFlash[(Offset & ~3U) / 4];
}

1
sram-overlay.h
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@ -19,6 +19,7 @@
#include <stdbool.h>
#include <stdint.h>
#include "driver/flash.h"
extern uint32_t overlay_FLASH_MainClock __attribute__((section(".srambss")));