mirror of
https://github.com/OneOfEleven/uv-k5-firmware-custom.git
synced 2025-04-27 22:01:26 +03:00
some fixes
This commit is contained in:
OneOfEleven
parent
cfe64c66b3
commit
78da1d5610
2
Makefile
2
Makefile
@ -258,7 +258,7 @@ CFLAGS =
|
||||
|
||||
ifeq ($(ENABLE_CLANG),0)
|
||||
#CFLAGS += -Os -Wall -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c11 -MMD
|
||||
CFLAGS += -Os -Werror -mcpu=cortex-m0 -fmodulo-sched -freorder-blocks-algorithm=stc -std=c11 -MMD
|
||||
CFLAGS += -Os -Werror -mcpu=cortex-m0 -freorder-blocks-algorithm=stc -std=c11 -MMD
|
||||
else
|
||||
# Oz needed to make it fit on flash
|
||||
CFLAGS += -Oz -Werror -mcpu=cortex-m0 -fno-builtin -fshort-enums -fno-delete-null-pointer-checks -std=c11 -MMD
|
||||
|
||||
48
app/app.c
48
app/app.c
@ -1033,6 +1033,54 @@ void APP_process_radio_interrupts(void)
|
||||
UART_printf("squelch opened\r\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef ENABLE_MDC1200
|
||||
{
|
||||
const uint16_t sync_flags = BK4819_ReadRegister(0x0B);
|
||||
|
||||
// if (sync_flags & ((1u << 7) | (1u << 6)))
|
||||
// { // RX sync found (pos or neg version)
|
||||
// #if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG)
|
||||
// UART_printf("fsk rx sync\r\n");
|
||||
// #endif
|
||||
// }
|
||||
|
||||
if (sync_flags & (1u << 7))
|
||||
{ // RX sync neg found
|
||||
#if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG)
|
||||
UART_printf("fsk rx sync neg\r\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
if (sync_flags & (1u << 6))
|
||||
{ // RX sync pos found
|
||||
#if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG)
|
||||
UART_printf("fsk rx sync pos\r\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
if (interrupt_bits & BK4819_REG_02_FSK_RX_SYNC)
|
||||
{
|
||||
#if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG)
|
||||
UART_printf("fsk rx sync\r\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
if (interrupt_bits & BK4819_REG_02_FSK_RX_FINISHED)
|
||||
{
|
||||
#if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG)
|
||||
UART_printf("fsk rx finished\r\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
if (interrupt_bits & BK4819_REG_02_FSK_FIFO_ALMOST_FULL)
|
||||
{
|
||||
#if defined(ENABLE_UART) && defined(ENABLE_UART_DEBUG)
|
||||
UART_printf("fsk rx almost full\r\n");
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
106
driver/bk4819.c
106
driver/bk4819.c
@ -889,9 +889,11 @@ void BK4819_RX_TurnOn(void)
|
||||
//
|
||||
BK4819_WriteRegister(0x37, 0x1F0F); // 0001 1111 0000 1111
|
||||
|
||||
// Turn off everything
|
||||
// turn everything off
|
||||
BK4819_WriteRegister(0x30, 0);
|
||||
|
||||
// and on again ..
|
||||
//
|
||||
// Enable VCO Calibration
|
||||
// Enable RX Link
|
||||
// Enable AF DAC
|
||||
@ -901,7 +903,7 @@ void BK4819_RX_TurnOn(void)
|
||||
// Disable TX DSP
|
||||
// Enable RX DSP
|
||||
//
|
||||
BK4819_WriteRegister(0x30, 0xbff1); // 1 0 1111 1 1 1111 0 0 0 1
|
||||
BK4819_WriteRegister(0x30, 0xBFF1); // 1 0 1111 1 1 1111 0 0 0 1
|
||||
}
|
||||
|
||||
void BK4819_set_rf_filter_path(uint32_t Frequency)
|
||||
@ -1784,6 +1786,27 @@ uint8_t BK4819_GetCTCType(void)
|
||||
return (BK4819_ReadRegister(0x0C) >> 10) & 3u;
|
||||
}
|
||||
|
||||
void BK4819_reset_fsk(void)
|
||||
{
|
||||
const uint16_t fsk_reg59 =
|
||||
(0u << 15) | // 0 or 1 1 = clear TX FIFO
|
||||
(0u << 14) | // 0 or 1 1 = clear RX FIFO
|
||||
(0u << 13) | // 0 or 1 1 = scramble
|
||||
(0u << 12) | // 0 or 1 1 = enable RX
|
||||
(0u << 11) | // 0 or 1 1 = enable TX
|
||||
(0u << 10) | // 0 or 1 1 = invert data when RX
|
||||
(0u << 9) | // 0 or 1 1 = invert data when TX
|
||||
(0u << 8) | // 0 or 1 ???
|
||||
(6u << 4) | // 0 ~ 15 preamble Length Selection
|
||||
(1u << 3) | // 0 or 1 sync length selection
|
||||
(0u << 0); // 0 ~ 7 ???
|
||||
|
||||
BK4819_WriteRegister(0x3F, 0); // disable interrupts
|
||||
BK4819_WriteRegister(0x59, (1u << 15) | (1u << 14) | fsk_reg59); // clear FIFO's
|
||||
BK4819_WriteRegister(0x59, (0u << 15) | (0u << 14) | fsk_reg59);
|
||||
BK4819_Idle();
|
||||
}
|
||||
|
||||
#ifdef ENABLE_AIRCOPY
|
||||
void BK4819_SetupAircopy(const unsigned int packet_size)
|
||||
{
|
||||
@ -1898,30 +1921,7 @@ uint8_t BK4819_GetCTCType(void)
|
||||
//
|
||||
BK4819_WriteRegister(0x5D, ((packet_size - 1) << 8));
|
||||
}
|
||||
#endif
|
||||
|
||||
void BK4819_reset_fsk(void)
|
||||
{
|
||||
const uint16_t fsk_reg59 =
|
||||
(0u << 15) | // 0 or 1 1 = clear TX FIFO
|
||||
(0u << 14) | // 0 or 1 1 = clear RX FIFO
|
||||
(0u << 13) | // 0 or 1 1 = scramble
|
||||
(0u << 12) | // 0 or 1 1 = enable RX
|
||||
(0u << 11) | // 0 or 1 1 = enable TX
|
||||
(0u << 10) | // 0 or 1 1 = invert data when RX
|
||||
(0u << 9) | // 0 or 1 1 = invert data when TX
|
||||
(0u << 8) | // 0 or 1 ???
|
||||
(6u << 4) | // 0 ~ 15 preamble Length Selection
|
||||
(1u << 3) | // 0 or 1 sync length selection
|
||||
(0u << 0); // 0 ~ 7 ???
|
||||
|
||||
BK4819_WriteRegister(0x3F, 0); // disable interrupts
|
||||
BK4819_WriteRegister(0x59, (1u << 15) | (1u << 14) | fsk_reg59); // clear FIFO's
|
||||
BK4819_WriteRegister(0x59, (0u << 15) | (0u << 14) | fsk_reg59);
|
||||
BK4819_Idle();
|
||||
}
|
||||
|
||||
#ifdef ENABLE_AIRCOPY
|
||||
void BK4819_start_aircopy_fsk_rx(const unsigned int packet_size)
|
||||
{
|
||||
uint16_t fsk_reg59;
|
||||
@ -1988,13 +1988,13 @@ void BK4819_reset_fsk(void)
|
||||
(1u << 3) | // 0 or 1 sync length selection
|
||||
(0u << 0); // 0 ~ 7 ???
|
||||
|
||||
BK4819_WriteRegister(0x59, (1u << 14) | fsk_reg59); // clear RX fifo
|
||||
BK4819_WriteRegister(0x59, (1u << 15) | (1u << 14) | fsk_reg59); // clear FIFO's
|
||||
BK4819_WriteRegister(0x59, (1u << 13) | (1u << 12) | fsk_reg59); // enable scrambler, enable RX
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_MDC1200
|
||||
void BK4819_enable_mdc1200_ffsk_rx(const bool enable)
|
||||
void BK4819_enable_mdc1200_rx(const bool enable)
|
||||
{
|
||||
// REG_70
|
||||
//
|
||||
@ -2087,7 +2087,20 @@ void BK4819_reset_fsk(void)
|
||||
|
||||
if (enable)
|
||||
{
|
||||
BK4819_WriteRegister(0x70, // 0 0000000 1 1100000
|
||||
const uint16_t fsk_reg59 =
|
||||
(0u << 15) | // 1 = clear TX FIFO
|
||||
(0u << 14) | // 1 = clear RX FIFO
|
||||
(0u << 13) | // 1 = scramble
|
||||
(0u << 12) | // 1 = enable RX
|
||||
(0u << 11) | // 1 = enable TX
|
||||
(0u << 10) | // 1 = invert data when RX
|
||||
(0u << 9) | // 1 = invert data when TX
|
||||
(0u << 8) | // ???
|
||||
(0u << 4) | // 0 ~ 15 preamble length selection .. mdc1200 does not send bit reversals :(
|
||||
(1u << 3) | // 0/1 sync length selection
|
||||
(0u << 0); // 0 ~ 7 ???
|
||||
|
||||
BK4819_WriteRegister(0x70,
|
||||
( 0u << 15) | // 0
|
||||
( 0u << 8) | // 0
|
||||
( 1u << 7) | // 1
|
||||
@ -2095,7 +2108,7 @@ void BK4819_reset_fsk(void)
|
||||
|
||||
BK4819_WriteRegister(0x72, ((1200u * 103244) + 5000) / 10000); // with rounding
|
||||
|
||||
BK4819_WriteRegister(0x58, // 0x37C3); 001 101 11 11 00 001 1
|
||||
BK4819_WriteRegister(0x58,
|
||||
(1u << 13) | // 1 FSK TX mode selection
|
||||
// 0 = FSK 1.2K and FSK 2.4K TX .. no tones, direct FM
|
||||
// 1 = FFSK 1200 / 1800 TX
|
||||
@ -2142,10 +2155,35 @@ void BK4819_reset_fsk(void)
|
||||
// 0 = disable
|
||||
// 1 = enable
|
||||
|
||||
// enable CRC ???
|
||||
BK4819_WriteRegister(0x5C, 0x5665); // 010101100 1 100101
|
||||
// 0000 0100 1000 1101 1011 1111 0110 0110 0101 1000
|
||||
// 0 4 8 D B F 6 6 5 8
|
||||
//
|
||||
// REG_5A
|
||||
//
|
||||
// <15:8> sync byte 0
|
||||
// < 7:0> sync byte 1
|
||||
BK4819_WriteRegister(0x5A, 0x8DBF);
|
||||
// <15:8> sync byte 2
|
||||
// < 7:0> sync byte 3
|
||||
BK4819_WriteRegister(0x5B, 0x6658);
|
||||
|
||||
BK4819_WriteRegister(0x5D, (15u << 8)); // packet size (16 bytes)
|
||||
// disable CRC
|
||||
BK4819_WriteRegister(0x5C, 0x5625 | (0u << 6));
|
||||
|
||||
// packet size (14 bytes)
|
||||
BK4819_WriteRegister(0x5D, ((14u - 1) << 8));
|
||||
|
||||
// clear FIFO's then enable RX
|
||||
BK4819_WriteRegister(0x59, (1u << 15) | (1u << 14) | fsk_reg59);
|
||||
BK4819_WriteRegister(0x59, (1u << 12) | fsk_reg59);
|
||||
|
||||
// clear interrupt flags
|
||||
BK4819_WriteRegister(0x02, 0);
|
||||
|
||||
BK4819_RX_TurnOn();
|
||||
|
||||
// enable interrupts
|
||||
BK4819_WriteRegister(0x3F, BK4819_ReadRegister(0x3F) | BK4819_REG_3F_FSK_RX_SYNC | BK4819_REG_3F_FSK_RX_FINISHED | BK4819_REG_3F_FSK_FIFO_ALMOST_FULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -2383,8 +2421,8 @@ void BK4819_reset_fsk(void)
|
||||
// Set entire packet length (not including the pre-amble and sync bytes we can't seem to disable)
|
||||
BK4819_WriteRegister(0x5D, ((size - 1) << 8));
|
||||
|
||||
BK4819_WriteRegister(0x59, (1u << 15) | fsk_reg59); // clear TX fifo by setting the FIFO reset bit
|
||||
BK4819_WriteRegister(0x59, (0u << 15) | fsk_reg59); // release the reset bit
|
||||
BK4819_WriteRegister(0x59, (1u << 15) | (1u << 14) | fsk_reg59); // clear FIFO's
|
||||
BK4819_WriteRegister(0x59, fsk_reg59); // release the FIFO reset
|
||||
|
||||
// REG_5A
|
||||
//
|
||||
|
||||
@ -163,7 +163,7 @@ uint8_t BK4819_GetCTCType(void);
|
||||
void BK4819_PlayRoger(void);
|
||||
|
||||
#ifdef ENABLE_MDC1200
|
||||
void BK4819_enable_mdc1200_ffsk_rx(const bool enable);
|
||||
void BK4819_enable_mdc1200_rx(const bool enable);
|
||||
void BK4819_send_MDC1200(const uint8_t op, const uint8_t arg, const uint16_t id);
|
||||
#endif
|
||||
|
||||
|
||||
26
driver/crc.c
26
driver/crc.c
@ -31,19 +31,21 @@ void CRC_Init(void)
|
||||
CRC_IV = 0;
|
||||
}
|
||||
|
||||
void CRC_InitReverse(void)
|
||||
{
|
||||
CRC_CR = 0
|
||||
| CRC_CR_CRC_EN_BITS_DISABLE
|
||||
| CRC_CR_INPUT_REV_BITS_NORMAL
|
||||
| CRC_CR_INPUT_INV_BITS_BIT_INVERTED
|
||||
| CRC_CR_OUTPUT_REV_BITS_REVERSED
|
||||
| CRC_CR_OUTPUT_INV_BITS_BIT_INVERTED
|
||||
| CRC_CR_DATA_WIDTH_BITS_8
|
||||
| CRC_CR_CRC_SEL_BITS_CRC_16_CCITT;
|
||||
#ifdef ENABLE_MDC1200
|
||||
void CRC_InitReverse(void)
|
||||
{
|
||||
CRC_CR =
|
||||
CRC_CR_CRC_EN_BITS_DISABLE |
|
||||
CRC_CR_INPUT_REV_BITS_NORMAL |
|
||||
CRC_CR_INPUT_INV_BITS_BIT_INVERTED |
|
||||
CRC_CR_OUTPUT_REV_BITS_REVERSED |
|
||||
CRC_CR_OUTPUT_INV_BITS_BIT_INVERTED |
|
||||
CRC_CR_DATA_WIDTH_BITS_8 |
|
||||
CRC_CR_CRC_SEL_BITS_CRC_16_CCITT;
|
||||
|
||||
CRC_IV = 0;
|
||||
}
|
||||
CRC_IV = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
uint16_t CRC_Calculate(const void *buffer, const unsigned int size)
|
||||
{
|
||||
|
||||
@ -20,7 +20,9 @@
|
||||
#include <stdint.h>
|
||||
|
||||
void CRC_Init(void);
|
||||
void CRC_InitReverse(void);
|
||||
#ifdef ENABLE_MDC1200
|
||||
void CRC_InitReverse(void);
|
||||
#endif
|
||||
uint16_t CRC_Calculate(const void *buffer, const unsigned int size);
|
||||
|
||||
#endif
|
||||
|
||||
BIN
firmware.bin
BIN
firmware.bin
Binary file not shown.
Binary file not shown.
@ -192,6 +192,10 @@ void FUNCTION_Select(function_type_t Function)
|
||||
g_dual_watch_delay_10ms = g_eeprom.scan_hold_time_500ms * 50;
|
||||
}
|
||||
|
||||
#ifdef ENABLE_MDC1200
|
||||
BK4819_enable_mdc1200_rx(false);
|
||||
#endif
|
||||
|
||||
// if DTMF is enabled when TX'ing, it changes the TX audio filtering ! .. 1of11
|
||||
// so MAKE SURE that DTMF is disabled - until needed
|
||||
BK4819_DisableDTMF();
|
||||
|
||||
89
mdc1200.c
89
mdc1200.c
@ -1,13 +1,12 @@
|
||||
|
||||
#include <string.h>
|
||||
|
||||
#include "bsp/dp32g030/crc.h"
|
||||
#include "driver/crc.h"
|
||||
#include "driver/uart.h"
|
||||
#include "mdc1200.h"
|
||||
#include "misc.h"
|
||||
|
||||
#define FEC_K 7
|
||||
#define FEC_K 7 // R=1/2 K=7 convolutional coder
|
||||
|
||||
// **********************************************************
|
||||
|
||||
@ -16,7 +15,7 @@
|
||||
// >= 24-bit pre-amble
|
||||
// 40-bit sync
|
||||
//
|
||||
//static const uint8_t pre_amble[] = {0x00, 0x00, 0x00, 0x00, 0xCC}; / add some bit reversals just before the sync pattern
|
||||
//static const uint8_t pre_amble[] = {0x00, 0x00, 0x00, 0xCC}; / add some bit reversals just before the sync pattern
|
||||
static const uint8_t pre_amble[] = {0x00, 0x00, 0x00};
|
||||
static const uint8_t sync[] = {0x07, 0x09, 0x2a, 0x44, 0x6f};
|
||||
|
||||
@ -51,10 +50,21 @@ uint32_t bit_reverse_32(uint32_t n)
|
||||
// ************************************
|
||||
// common
|
||||
|
||||
#if 0
|
||||
#if 1
|
||||
|
||||
uint16_t compute_crc(const uint8_t *data, const unsigned int data_len)
|
||||
{ // using the reverse computation avoids having to reverse the bit order during and after
|
||||
{ // let the CPU's hardware do some work :)
|
||||
uint16_t crc;
|
||||
CRC_InitReverse();
|
||||
crc = CRC_Calculate(data, data_len);
|
||||
CRC_Init();
|
||||
return crc;
|
||||
}
|
||||
|
||||
#elif 1
|
||||
|
||||
uint16_t compute_crc(const uint8_t *data, const unsigned int data_len)
|
||||
{ // using the reverse computation and polynominal avoids having to reverse the bit order during and after
|
||||
unsigned int i;
|
||||
uint16_t crc = 0;
|
||||
for (i = 0; i < data_len; i++)
|
||||
@ -67,17 +77,6 @@ uint32_t bit_reverse_32(uint32_t n)
|
||||
return crc ^ 0xffff;
|
||||
}
|
||||
|
||||
#elif 1
|
||||
|
||||
uint16_t compute_crc(const uint8_t *data, const unsigned int data_len)
|
||||
{ // let the CPU do the crc for us :)
|
||||
uint16_t crc;
|
||||
CRC_InitReverse();
|
||||
crc = CRC_Calculate(data, data_len);
|
||||
CRC_Init();
|
||||
return crc;
|
||||
}
|
||||
|
||||
#else
|
||||
|
||||
uint16_t compute_crc(const uint8_t *data, const unsigned int data_len)
|
||||
@ -147,7 +146,7 @@ void error_correction(uint8_t *data)
|
||||
ii--;
|
||||
}
|
||||
if (ii >= 0)
|
||||
data[ii] ^= 1u << bn; // do it
|
||||
data[ii] ^= 1u << bn; // fix a bit
|
||||
syn ^= 0xA6; // 10100110
|
||||
}
|
||||
}
|
||||
@ -186,7 +185,7 @@ bool decode_data(uint8_t *data)
|
||||
unsigned int i;
|
||||
unsigned int k;
|
||||
unsigned int m;
|
||||
uint8_t deinterleaved[(FEC_K * 2) * 8];
|
||||
uint8_t deinterleaved[(FEC_K * 2) * 8]; // temp individual bit storage
|
||||
|
||||
// interleave order
|
||||
// 0, 16, 32, 48, 64, 80, 96,
|
||||
@ -216,7 +215,7 @@ bool decode_data(uint8_t *data)
|
||||
}
|
||||
}
|
||||
|
||||
// copy the de-interleaved bits back intoto the data buffer
|
||||
// copy the de-interleaved bits back into the data buffer
|
||||
for (i = 0, m = 0; i < (FEC_K * 2); i++)
|
||||
{
|
||||
unsigned int k;
|
||||
@ -228,7 +227,7 @@ bool decode_data(uint8_t *data)
|
||||
}
|
||||
}
|
||||
|
||||
// see if we can correct a couple of corrupted bits (if need be)
|
||||
// try to correct the odd corrupted bit
|
||||
error_correction(data);
|
||||
|
||||
// rx'ed de-interleaved data (min 14 bytes) looks like this ..
|
||||
@ -459,7 +458,7 @@ void MDC1200_reset_rx(void)
|
||||
{
|
||||
memset(&rx, 0, sizeof(rx));
|
||||
}
|
||||
|
||||
|
||||
bool MDC1200_process_rx(const uint8_t rx_byte, uint8_t *op, uint8_t *arg, uint16_t *unit_id)
|
||||
{
|
||||
unsigned int i;
|
||||
@ -470,7 +469,7 @@ bool MDC1200_process_rx(const uint8_t rx_byte, uint8_t *op, uint8_t *arg, uint16
|
||||
rx.prev_bit = rx.bit;
|
||||
|
||||
rx.bit = (rx_byte >> k) & 1u;
|
||||
|
||||
|
||||
if (rx.stage == 0)
|
||||
{ // scanning for the pre-amble
|
||||
rx.xor_bit = rx.bit & 1u;
|
||||
@ -481,12 +480,12 @@ bool MDC1200_process_rx(const uint8_t rx_byte, uint8_t *op, uint8_t *arg, uint16
|
||||
if (rx.inverted_sync)
|
||||
rx.xor_bit ^= 1u;
|
||||
}
|
||||
|
||||
|
||||
rx.shift_reg = (rx.shift_reg << 1) | (rx.xor_bit & 1u);
|
||||
rx.bit_count++;
|
||||
|
||||
|
||||
// *********
|
||||
|
||||
|
||||
if (rx.stage == 0)
|
||||
{ // looking for pre-amble
|
||||
if (rx.bit_count < 20 || (rx.shift_reg & 0xfffff) != 1u)
|
||||
@ -495,11 +494,11 @@ bool MDC1200_process_rx(const uint8_t rx_byte, uint8_t *op, uint8_t *arg, uint16
|
||||
rx.xor_bit = 1;
|
||||
rx.stage = 1;
|
||||
rx.bit_count = 1;
|
||||
|
||||
|
||||
//s.printf("%5u %2u %u pre-amble found", index, rx_bit_count, rx_packet_stage);
|
||||
//Memo1->Lines->Add(s);
|
||||
}
|
||||
|
||||
|
||||
if (rx.stage < 2)
|
||||
{
|
||||
//s.printf("%5u %3u %u ", index, rx_bit_count, rx_packet_stage);
|
||||
@ -514,21 +513,21 @@ bool MDC1200_process_rx(const uint8_t rx_byte, uint8_t *op, uint8_t *arg, uint16
|
||||
//}
|
||||
//Memo1->Lines->Add(s);
|
||||
}
|
||||
|
||||
|
||||
if (rx.stage == 1)
|
||||
{ // looking for the 40-bit sync pattern, it follows the 24-bit pre-amble
|
||||
|
||||
|
||||
const unsigned int sync_bit_ok_threshold = 32;
|
||||
|
||||
|
||||
if (rx.bit_count >= sync_bit_ok_threshold)
|
||||
{
|
||||
// 40-bit sync pattern
|
||||
uint64_t sync_nor = 0x07092a446fu; // normal
|
||||
uint64_t sync_inv = 0xffffffffffu ^ sync_nor; // bit inverted
|
||||
|
||||
|
||||
sync_nor ^= rx.shift_reg;
|
||||
sync_inv ^= rx.shift_reg;
|
||||
|
||||
|
||||
unsigned int nor_count = 0;
|
||||
unsigned int inv_count = 0;
|
||||
for (i = 40; i > 0; i--, sync_nor >>= 1, sync_inv >>= 1)
|
||||
@ -538,12 +537,12 @@ bool MDC1200_process_rx(const uint8_t rx_byte, uint8_t *op, uint8_t *arg, uint16
|
||||
}
|
||||
nor_count = 40 - nor_count;
|
||||
inv_count = 40 - inv_count;
|
||||
|
||||
|
||||
if (nor_count >= sync_bit_ok_threshold || inv_count >= sync_bit_ok_threshold)
|
||||
{ // good enough
|
||||
|
||||
|
||||
rx.inverted_sync = (inv_count > nor_count) ? true : false;
|
||||
|
||||
|
||||
//String s;
|
||||
//s.printf("%5u %2u %u sync found %s %u bits ",
|
||||
// index,
|
||||
@ -551,7 +550,7 @@ bool MDC1200_process_rx(const uint8_t rx_byte, uint8_t *op, uint8_t *arg, uint16
|
||||
// rx_packet_stage,
|
||||
// rx_inverted_sync ? "inv" : "nor",
|
||||
// rx_inverted_sync ? inv_count : nor_count);
|
||||
|
||||
|
||||
//for (int i = 4; i >= 0; i--)
|
||||
//{
|
||||
// String s2;
|
||||
@ -562,13 +561,13 @@ bool MDC1200_process_rx(const uint8_t rx_byte, uint8_t *op, uint8_t *arg, uint16
|
||||
// s += s2;
|
||||
//}
|
||||
//Memo1->Lines->Add(s);
|
||||
|
||||
|
||||
rx.data_index = 0;
|
||||
rx.bit_count = 0;
|
||||
rx.stage++;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
@ -581,14 +580,14 @@ bool MDC1200_process_rx(const uint8_t rx_byte, uint8_t *op, uint8_t *arg, uint16
|
||||
continue;
|
||||
|
||||
rx.bit_count = 0;
|
||||
|
||||
|
||||
// 55 55 55 55 55 55 55 07 09 2A 44 6F 94 9C 22 20 32 A4 1A 37 1E 3A 00 98 2C 84
|
||||
|
||||
|
||||
rx.data[rx.data_index++] = rx.shift_reg & 0xff; // save the last 8 bits
|
||||
|
||||
|
||||
if (rx.data_index < (FEC_K * 2))
|
||||
continue;
|
||||
|
||||
|
||||
// s.printf("%5u %3u %u %2u ", index, rx_bit_count, rx_packet_stage, rx_buffer.size());
|
||||
// for (i = 0; i < rx_data_index; i++)
|
||||
// {
|
||||
@ -598,7 +597,7 @@ bool MDC1200_process_rx(const uint8_t rx_byte, uint8_t *op, uint8_t *arg, uint16
|
||||
// s += s2;
|
||||
// }
|
||||
// Memo1->Lines->Add(s);
|
||||
|
||||
|
||||
if (!decode_data(rx.data))
|
||||
{
|
||||
MDC1200_reset_rx();
|
||||
@ -609,7 +608,7 @@ bool MDC1200_process_rx(const uint8_t rx_byte, uint8_t *op, uint8_t *arg, uint16
|
||||
*op = rx.data[0];
|
||||
*arg = rx.data[1];
|
||||
*unit_id = ((uint16_t)rx.data[3] << 8) | (rx.data[2] << 0);
|
||||
|
||||
|
||||
//s.printf("%5u %3u %u %2u decoded ", index, rx_bit_count, rx_packet_stage, rx_buffer.size());
|
||||
//for (i = 0; i < 14; i++)
|
||||
//{
|
||||
@ -622,7 +621,7 @@ bool MDC1200_process_rx(const uint8_t rx_byte, uint8_t *op, uint8_t *arg, uint16
|
||||
|
||||
// reset the detector
|
||||
MDC1200_reset_rx();
|
||||
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
5
radio.c
5
radio.c
@ -787,6 +787,11 @@ void RADIO_setup_registers(bool switch_to_function_foreground)
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef ENABLE_MDC1200
|
||||
BK4819_enable_mdc1200_rx(true);
|
||||
interrupt_mask |= BK4819_ReadRegister(0x3F) | BK4819_REG_3F_FSK_RX_SYNC | BK4819_REG_3F_FSK_RX_FINISHED | BK4819_REG_3F_FSK_FIFO_ALMOST_FULL;
|
||||
#endif
|
||||
|
||||
// enable/disable BK4819 selected interrupts
|
||||
BK4819_WriteRegister(0x3F, interrupt_mask);
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user