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README.md

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OneOfEleven
2023-09-16 07:55:09 +01:00
parent 1e3b26768e
commit a24facec25
4 changed files with 47 additions and 55 deletions
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48
sram-overlay.c
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@ -21,9 +21,9 @@
#include "sram-overlay.h"
static volatile uint32_t *pFlash = 0;
uint32_t overlay_FLASH_MainClock;
uint32_t overlay_FLASH_ClockMultiplier;
uint32_t overlay_0x20000478; // Nothing is using this???
uint32_t overlay_FLASH_MainClock;
uint32_t overlay_FLASH_ClockMultiplier;
uint32_t overlay_0x20000478; // Nothing is using this???
void overlay_FLASH_RebootToBootloader(void)
{
@ -94,16 +94,14 @@ uint32_t overlay_FLASH_ReadByAPB(uint32_t Offset)
{
uint32_t Data;
while (overlay_FLASH_IsBusy()) {
}
while (overlay_FLASH_IsBusy()) {}
overlay_FLASH_SetMode(FLASH_MODE_READ_APB);
FLASH_ADDR = Offset >> 2;
overlay_FLASH_Start();
while (overlay_FLASH_IsBusy()) {
}
while (overlay_FLASH_IsBusy()) {}
Data = FLASH_RDATA;
@ -120,11 +118,11 @@ void overlay_FLASH_SetArea(FLASH_AREA Area)
void overlay_FLASH_SetReadMode(FLASH_READ_MODE Mode)
{
if (Mode == FLASH_READ_MODE_1_CYCLE) {
if (Mode == FLASH_READ_MODE_1_CYCLE)
FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_READ_MD_MASK) | FLASH_CFG_READ_MD_BITS_1_CYCLE;
} else if (Mode == FLASH_READ_MODE_2_CYCLE) {
else
if (Mode == FLASH_READ_MODE_2_CYCLE)
FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_READ_MD_MASK) | FLASH_CFG_READ_MD_BITS_2_CYCLE;
}
}
void overlay_FLASH_SetEraseTime(void)
@ -135,8 +133,7 @@ void overlay_FLASH_SetEraseTime(void)
void overlay_FLASH_WakeFromDeepSleep(void)
{
FLASH_CFG = (FLASH_CFG & ~FLASH_CFG_DEEP_PD_MASK) | FLASH_CFG_DEEP_PD_BITS_NORMAL;
while (!overlay_FLASH_IsInitComplete()) {
}
while (!overlay_FLASH_IsInitComplete()) {}
}
void overlay_FLASH_SetMode(FLASH_MODE Mode)
@ -153,28 +150,20 @@ void overlay_SystemReset(void)
{
// Lifted from core_cm0.h to preserve function order in the object file.
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
__DSB(); // Ensure all outstanding memory accesses included buffered write are completed before reset
SCB->AIRCR = (0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | SCB_AIRCR_SYSRESETREQ_Msk;
__DSB(); // Ensure completion of memory access
for(;;) /* wait until reset */
{
for (;;) // wait until reset
__NOP();
}
}
uint32_t overlay_FLASH_ReadNvrWord(uint32_t Offset)
{
uint32_t Data;
overlay_FLASH_SetArea(FLASH_AREA_NVR);
Data = overlay_FLASH_ReadByAHB(Offset);
overlay_FLASH_SetArea(FLASH_AREA_MAIN);
return Data;
}
@ -189,22 +178,21 @@ void overlay_FLASH_ConfigureTrimValues(void)
SYSCON_CHIP_ID2 = overlay_FLASH_ReadByAPB(0xF020);
SYSCON_CHIP_ID3 = overlay_FLASH_ReadByAPB(0xF024);
SYSCON_RC_FREQ_DELTA = overlay_FLASH_ReadByAHB(0x07C8);
SYSCON_RC_FREQ_DELTA = overlay_FLASH_ReadByAHB(0x07C8);
SYSCON_VREF_VOLT_DELTA = overlay_FLASH_ReadByAHB(0x07C4);
PMU_TRIM_POW0 = overlay_FLASH_ReadByAHB(0x07E4);
PMU_TRIM_POW1 = overlay_FLASH_ReadByAHB(0x07E0);
PMU_TRIM_RCHF = overlay_FLASH_ReadByAHB(0x07D8);
PMU_TRIM_RCLF = overlay_FLASH_ReadByAHB(0x07D4);
PMU_TRIM_OPA = overlay_FLASH_ReadByAHB(0x07D0);
PMU_TRIM_PLL = overlay_FLASH_ReadByAHB(0x07CC);
PMU_TRIM_OPA = overlay_FLASH_ReadByAHB(0x07D0);
PMU_TRIM_PLL = overlay_FLASH_ReadByAHB(0x07CC);
overlay_0x20000478 = overlay_FLASH_ReadByAHB(0x07B8);
Data = overlay_FLASH_ReadByAHB(0x07BC);
Data = overlay_FLASH_ReadByAHB(0x07BC);
SYSCON_DEV_CLK_GATE = (SYSCON_DEV_CLK_GATE & ~SYSCON_DEV_CLK_GATE_SARADC_MASK) | SYSCON_DEV_CLK_GATE_SARADC_BITS_ENABLE;
SARADC_CALIB_OFFSET = ((Data & 0xFFFF) << SARADC_CALIB_OFFSET_OFFSET_SHIFT) & SARADC_CALIB_OFFSET_OFFSET_MASK;
SARADC_CALIB_KD = (((Data >> 16) & 0xFFFF) << SARADC_CALIB_KD_KD_SHIFT) & SARADC_CALIB_KD_KD_MASK;
SARADC_CALIB_KD = (((Data >> 16) & 0xFFFF) << SARADC_CALIB_KD_KD_SHIFT) & SARADC_CALIB_KD_KD_MASK;
overlay_FLASH_SetArea(FLASH_AREA_MAIN);
}