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Code Issues Releases Activity

Fixed floating point handlers for qword operands and added missing FCOM ST(0), ST(i) handler

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This commit is contained in:
bird_egop
2025-04-18 00:44:57 +03:00
parent e6e3e886c8
commit 66f9e838ad
12 changed files with 156 additions and 38 deletions
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4
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FaddFloat64Handler.cs
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@ -51,8 +51,8 @@ public class FaddFloat64Handler : InstructionHandler
return false;
}
// Read the ModR/M byte using the specialized FPU method
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu();
// Read the ModR/M byte using the specialized FPU method for 64-bit operands
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64();
// Verify reg field is 0 (FADD)
if (reg != 0)

2
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivFloat64Handler.cs
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@ -52,7 +52,7 @@ public class FdivFloat64Handler : InstructionHandler
}
// Read the ModR/M byte using the specialized FPU method
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu();
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64();
// Set the instruction type
instruction.Type = InstructionType.Fdiv;

2
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivrFloat64Handler.cs
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@ -52,7 +52,7 @@ public class FdivrFloat64Handler : InstructionHandler
}
// Read the ModR/M byte using the specialized FPU method
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu();
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64();
// Set the instruction type
instruction.Type = InstructionType.Fdivr;

4
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FmulFloat64Handler.cs
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@ -51,8 +51,8 @@ public class FmulFloat64Handler : InstructionHandler
return false;
}
// Read the ModR/M byte using the specialized FPU method
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu();
// Read the ModR/M byte using the specialized FPU method for 64-bit operands
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64();
// Set the instruction type
instruction.Type = InstructionType.Fmul;

2
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FsubFloat64Handler.cs
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@ -52,7 +52,7 @@ public class FsubFloat64Handler : InstructionHandler
}
// Read the ModR/M byte using the specialized FPU method
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu();
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64();
// Set the instruction type
instruction.Type = InstructionType.Fsub;

2
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FsubrFloat64Handler.cs
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@ -52,7 +52,7 @@ public class FsubrFloat64Handler : InstructionHandler
}
// Read the ModR/M byte using the specialized FPU method
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu();
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64();
// Set the instruction type
instruction.Type = InstructionType.Fsubr;

2
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomFloat64Handler.cs
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@ -52,7 +52,7 @@ public class FcomFloat64Handler : InstructionHandler
}
// Read the ModR/M byte using the specialized FPU method
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu();
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64();
// Set the instruction type
instruction.Type = InstructionType.Fcom;

89
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcomSt0Handler.cs Normal file
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@ -0,0 +1,89 @@
namespace X86Disassembler.X86.Handlers.FloatingPoint.Comparison;
using X86Disassembler.X86.Operands;
/// <summary>
/// Handler for FCOM ST(0), ST(i) instruction (D8 D0-D7)
/// </summary>
public class FcomSt0Handler : InstructionHandler
{
/// <summary>
/// Initializes a new instance of the FcomSt0Handler class
/// </summary>
/// <param name="decoder">The instruction decoder that owns this handler</param>
public FcomSt0Handler(InstructionDecoder decoder)
: base(decoder)
{
}
/// <summary>
/// Checks if this handler can decode the given opcode
/// </summary>
/// <param name="opcode">The opcode to check</param>
/// <returns>True if this handler can decode the opcode</returns>
public override bool CanHandle(byte opcode)
{
// FCOM ST(0), ST(i) is D8 D0-D7
if (opcode != 0xD8) return false;
if (!Decoder.CanReadByte())
{
return false;
}
// Check if the ModR/M byte has reg field = 2 and mod = 3
byte modRm = Decoder.PeakByte();
byte reg = (byte)((modRm >> 3) & 0x7);
byte mod = (byte)((modRm >> 6) & 0x3);
// Only handle register operands (mod = 3) with reg = 2
return reg == 2 && mod == 3;
}
/// <summary>
/// Decodes a FCOM ST(0), ST(i) instruction
/// </summary>
/// <param name="opcode">The opcode of the instruction</param>
/// <param name="instruction">The instruction object to populate</param>
/// <returns>True if the instruction was successfully decoded</returns>
public override bool Decode(byte opcode, Instruction instruction)
{
if (!Decoder.CanReadByte())
{
return false;
}
// Read the ModR/M byte
var (mod, reg, rm, _) = ModRMDecoder.ReadModRMFpu();
// Set the instruction type
instruction.Type = InstructionType.Fcom;
// Map rm field to FPU register index
FpuRegisterIndex stIndex = rm switch
{
FpuRegisterIndex.ST0 => FpuRegisterIndex.ST0,
FpuRegisterIndex.ST1 => FpuRegisterIndex.ST1,
FpuRegisterIndex.ST2 => FpuRegisterIndex.ST2,
FpuRegisterIndex.ST3 => FpuRegisterIndex.ST3,
FpuRegisterIndex.ST4 => FpuRegisterIndex.ST4,
FpuRegisterIndex.ST5 => FpuRegisterIndex.ST5,
FpuRegisterIndex.ST6 => FpuRegisterIndex.ST6,
FpuRegisterIndex.ST7 => FpuRegisterIndex.ST7,
_ => FpuRegisterIndex.ST0 // Default case, should not happen
};
// Create the FPU register operands
var st0Operand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0);
var stiOperand = OperandFactory.CreateFPURegisterOperand(stIndex);
// Set the structured operands
instruction.StructuredOperands =
[
st0Operand,
stiOperand
];
return true;
}
}

2
X86Disassembler/X86/Handlers/FloatingPoint/Comparison/FcompFloat64Handler.cs
View File

@ -52,7 +52,7 @@ public class FcompFloat64Handler : InstructionHandler
}
// Read the ModR/M byte using the specialized FPU method
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu();
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64();
// Set the instruction type
instruction.Type = InstructionType.Fcomp;

23
X86Disassembler/X86/Handlers/InstructionHandlerFactory.cs
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@ -458,15 +458,26 @@ public class InstructionHandlerFactory
_handlers.Add(new FloatingPoint.Comparison.FucomiHandler(_decoder)); // FUCOMI (DB E8-EF)
_handlers.Add(new FloatingPoint.Comparison.FcomiHandler(_decoder)); // FCOMI (DB F0-F7)
// D8 opcode handlers (register operations)
_handlers.Add(new FloatingPoint.Arithmetic.FaddRegisterHandler(_decoder)); // FADD ST(0), ST(i) (D8 C0-C7)
_handlers.Add(new FloatingPoint.Arithmetic.FmulRegisterHandler(_decoder)); // FMUL ST(0), ST(i) (D8 C8-CF)
_handlers.Add(new FloatingPoint.Comparison.FcomSt0Handler(_decoder)); // FCOM ST(0), ST(i) (D8 D0-D7)
_handlers.Add(new FloatingPoint.Arithmetic.FsubRegisterHandler(_decoder)); // FSUB ST(0), ST(i) (D8 E0-E7)
_handlers.Add(new FloatingPoint.Arithmetic.FsubrRegisterHandler(_decoder)); // FSUBR ST(0), ST(i) (D8 E8-EF)
_handlers.Add(new FloatingPoint.Arithmetic.FdivRegisterHandler(_decoder)); // FDIV ST(0), ST(i) (D8 F0-F7)
_handlers.Add(new FloatingPoint.Arithmetic.FdivrRegisterHandler(_decoder)); // FDIVR ST(0), ST(i) (D8 F8-FF)
// DC opcode handlers (register-register operations)
_handlers.Add(new FloatingPoint.Arithmetic.FaddRegisterHandler(_decoder)); // FADD ST(i), ST(0) (DC C0-C7)
_handlers.Add(new FloatingPoint.Arithmetic.FmulRegisterHandler(_decoder)); // FMUL ST(i), ST(0) (DC C8-CF)
_handlers.Add(new FloatingPoint.Arithmetic.FaddFloat64Handler(_decoder)); // FADD float64 (DC /0)
_handlers.Add(new FloatingPoint.Arithmetic.FmulFloat64Handler(_decoder)); // FMUL float64 (DC /1)
_handlers.Add(new FloatingPoint.Comparison.FcomFloat64Handler(_decoder)); // FCOM float64 (DC /2)
_handlers.Add(new FloatingPoint.Comparison.FcompFloat64Handler(_decoder)); // FCOMP float64 (DC /3)
_handlers.Add(new FloatingPoint.Arithmetic.FsubFloat64Handler(_decoder)); // FSUB float64 (DC /4)
_handlers.Add(new FloatingPoint.Arithmetic.FsubrFloat64Handler(_decoder)); // FSUBR float64 (DC /5)
_handlers.Add(new FloatingPoint.Arithmetic.FdivFloat64Handler(_decoder)); // FDIV float64 (DC /6)
_handlers.Add(new FloatingPoint.Arithmetic.FdivrFloat64Handler(_decoder)); // FDIVR float64 (DC /7)
_handlers.Add(new FloatingPoint.Comparison.FcomRegisterHandler(_decoder)); // FCOM ST(i), ST(0) (DC D0-D7)
_handlers.Add(new FloatingPoint.Comparison.FcompRegisterHandler(_decoder)); // FCOMP ST(i), ST(0) (DC D8-DF)
_handlers.Add(new FloatingPoint.Arithmetic.FsubRegisterHandler(_decoder)); // FSUB ST(i), ST(0) (DC E0-E7)
_handlers.Add(new FloatingPoint.Arithmetic.FsubrRegisterHandler(_decoder)); // FSUBR ST(i), ST(0) (DC E8-EF)
_handlers.Add(new FloatingPoint.Arithmetic.FdivRegisterHandler(_decoder)); // FDIV ST(i), ST(0) (DC F0-F7)
_handlers.Add(new FloatingPoint.Arithmetic.FdivrRegisterHandler(_decoder)); // FDIVR ST(i), ST(0) (DC F8-FF)
// DD opcode handlers (register operations)
_handlers.Add(new FloatingPoint.Control.FfreeHandler(_decoder)); // FFREE ST(i) (DD C0-C7)

24
X86Disassembler/X86/ModRMDecoder.cs
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@ -207,17 +207,33 @@ public class ModRMDecoder
public (byte mod, RegisterIndex reg, RegisterIndex rm, Operand operand) ReadModRM64() => ReadModRMInternal(true);
/// <summary>
/// Reads and decodes a ModR/M byte for FPU instructions
/// Reads and decodes a ModR/M byte for FPU instructions with 32-bit memory operands
/// </summary>
/// <returns>A tuple containing the mod, reg, rm fields (with rm as FpuRegisterIndex) and the decoded operand</returns>
public (byte mod, RegisterIndex reg, FpuRegisterIndex fpuRm, Operand operand) ReadModRMFpu()
public (byte mod, FpuRegisterIndex reg, FpuRegisterIndex rm, Operand operand) ReadModRMFpu()
{
var (mod, reg, rm, operand) = ReadModRMInternal(false);
// Convert the RegisterIndex rm to FpuRegisterIndex
FpuRegisterIndex fpuRm = (FpuRegisterIndex)(int)rm;
FpuRegisterIndex regIndex = (FpuRegisterIndex)reg;
FpuRegisterIndex rmIndex = (FpuRegisterIndex)rm;
return (mod, reg, fpuRm, operand);
return (mod, regIndex, rmIndex, operand);
}
/// <summary>
/// Reads and decodes a ModR/M byte for FPU instructions with 64-bit memory operands
/// </summary>
/// <returns>A tuple containing the mod, reg, rm fields (with rm as FpuRegisterIndex) and the decoded operand</returns>
public (byte mod, FpuRegisterIndex reg, FpuRegisterIndex rm, Operand operand) ReadModRMFpu64()
{
var (mod, reg, rm, operand) = ReadModRMInternal(true); // Use is64Bit=true for 64-bit operands
// Convert the RegisterIndex rm to FpuRegisterIndex
FpuRegisterIndex regIndex = (FpuRegisterIndex)reg;
FpuRegisterIndex rmIndex = (FpuRegisterIndex)rm;
return (mod, regIndex, rmIndex, operand);
}
/// <summary>

38
X86DisassemblerTests/TestData/fadd_tests.csv
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@ -24,22 +24,22 @@ DCC6;[{ "Type": "Fadd", "Operands": ["ST(6)", "ST(0)"] }]
DCC7;[{ "Type": "Fadd", "Operands": ["ST(7)", "ST(0)"] }]
# Memory operands
D8042510000000;[{ "Type": "Fadd", "Operands": ["dword ptr [0x10]"] }]
DC042510000000;[{ "Type": "Fadd", "Operands": ["qword ptr [0x10]"] }]
D80425;[{ "Type": "Fadd", "Operands": ["dword ptr [eax]"] }]
DC0425;[{ "Type": "Fadd", "Operands": ["qword ptr [eax]"] }]
D8041D;[{ "Type": "Fadd", "Operands": ["dword ptr [ebx]"] }]
DC041D;[{ "Type": "Fadd", "Operands": ["qword ptr [ebx]"] }]
D8042D;[{ "Type": "Fadd", "Operands": ["dword ptr [ebp]"] }]
DC042D;[{ "Type": "Fadd", "Operands": ["qword ptr [ebp]"] }]
D80510000000;[{ "Type": "Fadd", "Operands": ["dword ptr [0x10]"] }]
DC0510000000;[{ "Type": "Fadd", "Operands": ["qword ptr [0x10]"] }]
D800;[{ "Type": "Fadd", "Operands": ["dword ptr [eax]"] }]
DC00;[{ "Type": "Fadd", "Operands": ["qword ptr [eax]"] }]
D803;[{ "Type": "Fadd", "Operands": ["dword ptr [ebx]"] }]
DC03;[{ "Type": "Fadd", "Operands": ["qword ptr [ebx]"] }]
D84500;[{ "Type": "Fadd", "Operands": ["dword ptr [ebp+0x00]"] }]
DC4500;[{ "Type": "Fadd", "Operands": ["qword ptr [ebp+0x00]"] }]
# With segment override prefixes
26D80425;[{ "Type": "Fadd", "Operands": ["dword ptr es:[eax]"] }]
2ED80425;[{ "Type": "Fadd", "Operands": ["dword ptr cs:[eax]"] }]
36D80425;[{ "Type": "Fadd", "Operands": ["dword ptr ss:[eax]"] }]
3ED80425;[{ "Type": "Fadd", "Operands": ["dword ptr ds:[eax]"] }]
64D80425;[{ "Type": "Fadd", "Operands": ["dword ptr fs:[eax]"] }]
65D80425;[{ "Type": "Fadd", "Operands": ["dword ptr gs:[eax]"] }]
26D800;[{ "Type": "Fadd", "Operands": ["dword ptr es:[eax]"] }]
2ED800;[{ "Type": "Fadd", "Operands": ["dword ptr cs:[eax]"] }]
36D800;[{ "Type": "Fadd", "Operands": ["dword ptr ss:[eax]"] }]
3ED800;[{ "Type": "Fadd", "Operands": ["dword ptr ds:[eax]"] }]
64D800;[{ "Type": "Fadd", "Operands": ["dword ptr fs:[eax]"] }]
65D800;[{ "Type": "Fadd", "Operands": ["dword ptr gs:[eax]"] }]
# FADDP - Add floating point values and pop
DEC0;[{ "Type": "Faddp", "Operands": ["ST(0)", "ST(0)"] }]
@ -54,7 +54,9 @@ DEC7;[{ "Type": "Faddp", "Operands": ["ST(7)", "ST(0)"] }]
# FIADD - Add integer to floating point
DA042510000000;[{ "Type": "Fiadd", "Operands": ["dword ptr [0x10]"] }]
DE042510000000;[{ "Type": "Fiadd", "Operands": ["word ptr [0x10]"] }]
DA0425;[{ "Type": "Fiadd", "Operands": ["dword ptr [eax]"] }]
DE0425;[{ "Type": "Fiadd", "Operands": ["word ptr [eax]"] }]
DA041D;[{ "Type": "Fiadd", "Operands": ["dword ptr [ebx]"] }]
DE041D;[{ "Type": "Fiadd", "Operands": ["word ptr [ebx]"] }]
# Corrected FIADD tests
DA00;[{ "Type": "Fiadd", "Operands": ["dword ptr [eax]"] }]
DE00;[{ "Type": "Fiadd", "Operands": ["word ptr [eax]"] }]
DA03;[{ "Type": "Fiadd", "Operands": ["dword ptr [ebx]"] }]
DE03;[{ "Type": "Fiadd", "Operands": ["word ptr [ebx]"] }]

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