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Code Issues Releases Activity

Fixed floating point handlers for qword operands and added missing FCOM ST(0), ST(i) handler

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bird_egop
2025-04-18 00:44:57 +03:00
parent e6e3e886c8
commit 66f9e838ad
12 changed files with 156 additions and 38 deletions
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23
X86Disassembler/X86/Handlers/InstructionHandlerFactory.cs
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@ -458,15 +458,26 @@ public class InstructionHandlerFactory
_handlers.Add(new FloatingPoint.Comparison.FucomiHandler(_decoder)); // FUCOMI (DB E8-EF)
_handlers.Add(new FloatingPoint.Comparison.FcomiHandler(_decoder)); // FCOMI (DB F0-F7)
// D8 opcode handlers (register operations)
_handlers.Add(new FloatingPoint.Arithmetic.FaddRegisterHandler(_decoder)); // FADD ST(0), ST(i) (D8 C0-C7)
_handlers.Add(new FloatingPoint.Arithmetic.FmulRegisterHandler(_decoder)); // FMUL ST(0), ST(i) (D8 C8-CF)
_handlers.Add(new FloatingPoint.Comparison.FcomSt0Handler(_decoder)); // FCOM ST(0), ST(i) (D8 D0-D7)
_handlers.Add(new FloatingPoint.Arithmetic.FsubRegisterHandler(_decoder)); // FSUB ST(0), ST(i) (D8 E0-E7)
_handlers.Add(new FloatingPoint.Arithmetic.FsubrRegisterHandler(_decoder)); // FSUBR ST(0), ST(i) (D8 E8-EF)
_handlers.Add(new FloatingPoint.Arithmetic.FdivRegisterHandler(_decoder)); // FDIV ST(0), ST(i) (D8 F0-F7)
_handlers.Add(new FloatingPoint.Arithmetic.FdivrRegisterHandler(_decoder)); // FDIVR ST(0), ST(i) (D8 F8-FF)
// DC opcode handlers (register-register operations)
_handlers.Add(new FloatingPoint.Arithmetic.FaddRegisterHandler(_decoder)); // FADD ST(i), ST(0) (DC C0-C7)
_handlers.Add(new FloatingPoint.Arithmetic.FmulRegisterHandler(_decoder)); // FMUL ST(i), ST(0) (DC C8-CF)
_handlers.Add(new FloatingPoint.Arithmetic.FaddFloat64Handler(_decoder)); // FADD float64 (DC /0)
_handlers.Add(new FloatingPoint.Arithmetic.FmulFloat64Handler(_decoder)); // FMUL float64 (DC /1)
_handlers.Add(new FloatingPoint.Comparison.FcomFloat64Handler(_decoder)); // FCOM float64 (DC /2)
_handlers.Add(new FloatingPoint.Comparison.FcompFloat64Handler(_decoder)); // FCOMP float64 (DC /3)
_handlers.Add(new FloatingPoint.Arithmetic.FsubFloat64Handler(_decoder)); // FSUB float64 (DC /4)
_handlers.Add(new FloatingPoint.Arithmetic.FsubrFloat64Handler(_decoder)); // FSUBR float64 (DC /5)
_handlers.Add(new FloatingPoint.Arithmetic.FdivFloat64Handler(_decoder)); // FDIV float64 (DC /6)
_handlers.Add(new FloatingPoint.Arithmetic.FdivrFloat64Handler(_decoder)); // FDIVR float64 (DC /7)
_handlers.Add(new FloatingPoint.Comparison.FcomRegisterHandler(_decoder)); // FCOM ST(i), ST(0) (DC D0-D7)
_handlers.Add(new FloatingPoint.Comparison.FcompRegisterHandler(_decoder)); // FCOMP ST(i), ST(0) (DC D8-DF)
_handlers.Add(new FloatingPoint.Arithmetic.FsubRegisterHandler(_decoder)); // FSUB ST(i), ST(0) (DC E0-E7)
_handlers.Add(new FloatingPoint.Arithmetic.FsubrRegisterHandler(_decoder)); // FSUBR ST(i), ST(0) (DC E8-EF)
_handlers.Add(new FloatingPoint.Arithmetic.FdivRegisterHandler(_decoder)); // FDIV ST(i), ST(0) (DC F0-F7)
_handlers.Add(new FloatingPoint.Arithmetic.FdivrRegisterHandler(_decoder)); // FDIVR ST(i), ST(0) (DC F8-FF)
// DD opcode handlers (register operations)
_handlers.Add(new FloatingPoint.Control.FfreeHandler(_decoder)); // FFREE ST(i) (DD C0-C7)