mirror of
https://github.com/sampletext32/ParkanPlayground.git
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Updated instruction handlers to use Type and StructuredOperands instead of Mnemonic and Operands
This commit is contained in:
bird_egop
@ -1,3 +1,5 @@
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using X86Disassembler.X86.Operands;
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// <summary>
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@ -18,14 +20,25 @@ public class Float32OperationHandler : InstructionHandler
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"fdivr"
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];
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// Corresponding instruction types for each mnemonic
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private static readonly InstructionType[] InstructionTypes =
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[
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InstructionType.Fadd,
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InstructionType.Fmul,
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InstructionType.Fcom,
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InstructionType.Fcomp,
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InstructionType.Fsub,
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InstructionType.Fsubr,
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InstructionType.Fdiv,
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InstructionType.Fdivr
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];
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/// <summary>
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/// Initializes a new instance of the Float32OperationHandler class
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/// </summary>
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/// <param name="codeBuffer">The buffer containing the code to decode</param>
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/// <param name="decoder">The instruction decoder that owns this handler</param>
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/// <param name="length">The length of the buffer</param>
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public Float32OperationHandler(byte[] codeBuffer, InstructionDecoder decoder, int length)
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: base(codeBuffer, decoder, length)
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public Float32OperationHandler(InstructionDecoder decoder)
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: base(decoder)
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{
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}
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@ -53,20 +66,35 @@ public class Float32OperationHandler : InstructionHandler
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}
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// Read the ModR/M byte
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var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM();
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var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM();
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// Set the mnemonic based on the opcode and reg field
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instruction.Mnemonic = Mnemonics[(int)reg];
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// Set the instruction type based on the reg field
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instruction.Type = InstructionTypes[(int)reg];
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// For memory operands, set the operand
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if (mod != 3) // Memory operand
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{
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instruction.Operands = destOperand;
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// Ensure the memory operand has the correct size (32-bit float)
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operand.Size = 32;
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// Set the structured operands
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instruction.StructuredOperands =
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[
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operand
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];
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}
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else // Register operand (ST(i))
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{
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// For register operands, we need to handle the stack registers
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instruction.Operands = $"st(0), st({(int)rm})";
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var st0Operand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0); // ST(0)
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var stiOperand = OperandFactory.CreateFPURegisterOperand((FpuRegisterIndex)rm); // ST(i)
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// Set the structured operands
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instruction.StructuredOperands =
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[
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st0Operand,
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stiOperand
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];
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}
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return true;
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@ -1,3 +1,5 @@
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using X86Disassembler.X86.Operands;
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// <summary>
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@ -18,14 +20,25 @@ public class Float64OperationHandler : InstructionHandler
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"fdivr"
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];
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// Corresponding instruction types for each mnemonic
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private static readonly InstructionType[] InstructionTypes =
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[
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InstructionType.Fadd,
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InstructionType.Fmul,
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InstructionType.Fcom,
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InstructionType.Fcomp,
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InstructionType.Fsub,
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InstructionType.Fsubr,
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InstructionType.Fdiv,
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InstructionType.Fdivr
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];
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/// <summary>
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/// Initializes a new instance of the Float64OperationHandler class
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/// </summary>
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/// <param name="codeBuffer">The buffer containing the code to decode</param>
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/// <param name="decoder">The instruction decoder that owns this handler</param>
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/// <param name="length">The length of the buffer</param>
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public Float64OperationHandler(byte[] codeBuffer, InstructionDecoder decoder, int length)
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: base(codeBuffer, decoder, length)
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public Float64OperationHandler(InstructionDecoder decoder)
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: base(decoder)
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{
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}
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@ -53,20 +66,35 @@ public class Float64OperationHandler : InstructionHandler
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}
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// Read the ModR/M byte
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var (mod, reg, rm, destOperand) = ModRMDecoder.ReadModRM(true); // true for 64-bit operand
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var (mod, reg, rm, operand) = ModRMDecoder.ReadModRM(true); // true for 64-bit operand
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// Set the mnemonic based on the opcode and reg field
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instruction.Mnemonic = Mnemonics[(int)reg];
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// Set the instruction type based on the reg field
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instruction.Type = InstructionTypes[(int)reg];
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// For memory operands, set the operand
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if (mod != 3) // Memory operand
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{
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instruction.Operands = destOperand;
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// Ensure the memory operand has the correct size (64-bit float)
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operand.Size = 64;
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// Set the structured operands
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instruction.StructuredOperands =
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[
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operand
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];
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}
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else // Register operand (ST(i))
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{
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// For DC C0-DC FF, the operands are reversed: ST(i), ST(0)
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instruction.Operands = $"st({(int)rm}), st(0)";
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var stiOperand = OperandFactory.CreateFPURegisterOperand((FpuRegisterIndex)rm); // ST(i)
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var st0Operand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0); // ST(0)
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// Set the structured operands
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instruction.StructuredOperands =
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[
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stiOperand,
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st0Operand
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];
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}
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return true;
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@ -1,5 +1,7 @@
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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using X86Disassembler.X86.Operands;
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/// <summary>
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/// Handler for FNSTSW AX instruction (0xDF 0xE0)
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/// </summary>
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@ -8,11 +10,9 @@ public class FnstswHandler : InstructionHandler
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/// <summary>
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/// Initializes a new instance of the FnstswHandler class
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/// </summary>
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/// <param name="codeBuffer">The buffer containing the code to decode</param>
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/// <param name="decoder">The instruction decoder that owns this handler</param>
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/// <param name="length">The length of the buffer</param>
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public FnstswHandler(byte[] codeBuffer, InstructionDecoder decoder, int length)
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: base(codeBuffer, decoder, length)
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public FnstswHandler(InstructionDecoder decoder)
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: base(decoder)
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{
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}
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@ -24,20 +24,18 @@ public class FnstswHandler : InstructionHandler
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public override bool CanHandle(byte opcode)
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{
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// FNSTSW is a two-byte opcode (0xDF 0xE0)
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if (opcode == 0xDF)
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{
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if (!Decoder.CanReadByte())
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{
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return false;
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}
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if (opcode != 0xDF) return false;
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if (CodeBuffer[Decoder.GetPosition()] == 0xE0)
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{
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return true;
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}
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if (!Decoder.CanReadByte())
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{
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return false;
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}
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if (Decoder.PeakByte() != 0xE0)
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return false;
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return false;
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return true;
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}
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/// <summary>
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@ -61,9 +59,17 @@ public class FnstswHandler : InstructionHandler
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return false;
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}
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// Set the mnemonic and operands
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instruction.Mnemonic = "fnstsw";
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instruction.Operands = "ax";
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// Set the instruction type
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instruction.Type = InstructionType.Fnstsw;
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// Create the AX register operand
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var axOperand = OperandFactory.CreateRegisterOperand(RegisterIndex.A, 16);
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// Set the structured operands
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instruction.StructuredOperands =
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[
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axOperand
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];
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return true;
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}
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@ -1,3 +1,5 @@
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using X86Disassembler.X86.Operands;
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namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// <summary>
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@ -5,95 +7,93 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
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/// </summary>
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public class Int16OperationHandler : InstructionHandler
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{
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// Memory operand mnemonics for DE opcode - operations on int16
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private static readonly string[] MemoryMnemonics =
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// Memory operand instruction types for DE opcode - operations on int16
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private static readonly InstructionType[] MemoryInstructionTypes =
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[
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"fiadd", // 0
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"fimul", // 1
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"ficom", // 2
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"ficomp", // 3
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"fisub", // 4
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"fisubr", // 5
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"fidiv", // 6
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"fidivr" // 7
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InstructionType.Unknown, // fiadd - not in enum
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InstructionType.Unknown, // fimul - not in enum
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InstructionType.Unknown, // ficom - not in enum
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InstructionType.Unknown, // ficomp - not in enum
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InstructionType.Unknown, // fisub - not in enum
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InstructionType.Unknown, // fisubr - not in enum
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InstructionType.Unknown, // fidiv - not in enum
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InstructionType.Unknown // fidivr - not in enum
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];
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// Register-register operations mapping (mod=3)
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private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
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private static readonly Dictionary<(int Reg, int Rm), (InstructionType Type, FpuRegisterIndex DestIndex, FpuRegisterIndex? SrcIndex)> RegisterOperations = new()
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{
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// FADDP st(i), st(0)
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{ (RegisterIndex.A, RegisterIndex.A), ("faddp", "st(0), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.C), ("faddp", "st(1), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.D), ("faddp", "st(2), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.B), ("faddp", "st(3), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.Sp), ("faddp", "st(4), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.Bp), ("faddp", "st(5), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.Si), ("faddp", "st(6), st(0)") },
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{ (RegisterIndex.A, RegisterIndex.Di), ("faddp", "st(7), st(0)") },
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{ (0, 0), (InstructionType.Fadd, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (0, 1), (InstructionType.Fadd, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (0, 2), (InstructionType.Fadd, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (0, 3), (InstructionType.Fadd, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (0, 4), (InstructionType.Fadd, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (0, 5), (InstructionType.Fadd, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (0, 6), (InstructionType.Fadd, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (0, 7), (InstructionType.Fadd, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// FMULP st(i), st(0)
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{ (RegisterIndex.B, RegisterIndex.A), ("fmulp", "st(0), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.C), ("fmulp", "st(1), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.D), ("fmulp", "st(2), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.B), ("fmulp", "st(3), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.Sp), ("fmulp", "st(4), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.Bp), ("fmulp", "st(5), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.Si), ("fmulp", "st(6), st(0)") },
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{ (RegisterIndex.B, RegisterIndex.Di), ("fmulp", "st(7), st(0)") },
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{ (1, 0), (InstructionType.Fmul, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (1, 1), (InstructionType.Fmul, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (1, 2), (InstructionType.Fmul, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (1, 3), (InstructionType.Fmul, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (1, 4), (InstructionType.Fmul, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (1, 5), (InstructionType.Fmul, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (1, 6), (InstructionType.Fmul, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (1, 7), (InstructionType.Fmul, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// Special cases
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{ (RegisterIndex.C, RegisterIndex.B), ("fcomp", "") },
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{ (RegisterIndex.D, RegisterIndex.B), ("fcompp", "") },
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{ (2, 3), (InstructionType.Fcomp, FpuRegisterIndex.ST0, null) },
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{ (3, 3), (InstructionType.Fcompp, FpuRegisterIndex.ST0, null) },
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// FSUBP st(i), st(0)
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{ (RegisterIndex.Si, RegisterIndex.A), ("fsubp", "st(0), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.C), ("fsubp", "st(1), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.D), ("fsubp", "st(2), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.B), ("fsubp", "st(3), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.Sp), ("fsubp", "st(4), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.Bp), ("fsubp", "st(5), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.Si), ("fsubp", "st(6), st(0)") },
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{ (RegisterIndex.Si, RegisterIndex.Di), ("fsubp", "st(7), st(0)") },
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{ (6, 0), (InstructionType.Fsub, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (6, 1), (InstructionType.Fsub, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (6, 2), (InstructionType.Fsub, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (6, 3), (InstructionType.Fsub, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (6, 4), (InstructionType.Fsub, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (6, 5), (InstructionType.Fsub, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (6, 6), (InstructionType.Fsub, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (6, 7), (InstructionType.Fsub, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// FSUBRP st(i), st(0)
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{ (RegisterIndex.Di, RegisterIndex.A), ("fsubrp", "st(0), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.C), ("fsubrp", "st(1), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.D), ("fsubrp", "st(2), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.B), ("fsubrp", "st(3), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.Sp), ("fsubrp", "st(4), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.Bp), ("fsubrp", "st(5), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.Si), ("fsubrp", "st(6), st(0)") },
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{ (RegisterIndex.Di, RegisterIndex.Di), ("fsubrp", "st(7), st(0)") },
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{ (7, 0), (InstructionType.Fsubr, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (7, 1), (InstructionType.Fsubr, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (7, 2), (InstructionType.Fsubr, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (7, 3), (InstructionType.Fsubr, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (7, 4), (InstructionType.Fsubr, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (7, 5), (InstructionType.Fsubr, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (7, 6), (InstructionType.Fsubr, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (7, 7), (InstructionType.Fsubr, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// FDIVP st(i), st(0)
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{ (RegisterIndex.Sp, RegisterIndex.A), ("fdivp", "st(0), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.C), ("fdivp", "st(1), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.D), ("fdivp", "st(2), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.B), ("fdivp", "st(3), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.Sp), ("fdivp", "st(4), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.Bp), ("fdivp", "st(5), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.Si), ("fdivp", "st(6), st(0)") },
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{ (RegisterIndex.Sp, RegisterIndex.Di), ("fdivp", "st(7), st(0)") },
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{ (4, 0), (InstructionType.Fdiv, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
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{ (4, 1), (InstructionType.Fdiv, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
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{ (4, 2), (InstructionType.Fdiv, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
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{ (4, 3), (InstructionType.Fdiv, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
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{ (4, 4), (InstructionType.Fdiv, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
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{ (4, 5), (InstructionType.Fdiv, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
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{ (4, 6), (InstructionType.Fdiv, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
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{ (4, 7), (InstructionType.Fdiv, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) },
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// FDIVRP st(i), st(0)
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{ (RegisterIndex.Bp, RegisterIndex.A), ("fdivrp", "st(0), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.C), ("fdivrp", "st(1), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.D), ("fdivrp", "st(2), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.B), ("fdivrp", "st(3), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.Sp), ("fdivrp", "st(4), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.Bp), ("fdivrp", "st(5), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.Si), ("fdivrp", "st(6), st(0)") },
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{ (RegisterIndex.Bp, RegisterIndex.Di), ("fdivrp", "st(7), st(0)") }
|
||||
{ (5, 0), (InstructionType.Fdivr, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (5, 1), (InstructionType.Fdivr, FpuRegisterIndex.ST1, FpuRegisterIndex.ST0) },
|
||||
{ (5, 2), (InstructionType.Fdivr, FpuRegisterIndex.ST2, FpuRegisterIndex.ST0) },
|
||||
{ (5, 3), (InstructionType.Fdivr, FpuRegisterIndex.ST3, FpuRegisterIndex.ST0) },
|
||||
{ (5, 4), (InstructionType.Fdivr, FpuRegisterIndex.ST4, FpuRegisterIndex.ST0) },
|
||||
{ (5, 5), (InstructionType.Fdivr, FpuRegisterIndex.ST5, FpuRegisterIndex.ST0) },
|
||||
{ (5, 6), (InstructionType.Fdivr, FpuRegisterIndex.ST6, FpuRegisterIndex.ST0) },
|
||||
{ (5, 7), (InstructionType.Fdivr, FpuRegisterIndex.ST7, FpuRegisterIndex.ST0) }
|
||||
};
|
||||
|
||||
/// <summary>
|
||||
/// Initializes a new instance of the Int16OperationHandler class
|
||||
/// </summary>
|
||||
/// <param name="codeBuffer">The buffer containing the code to decode</param>
|
||||
/// <param name="decoder">The instruction decoder that owns this handler</param>
|
||||
/// <param name="length">The length of the buffer</param>
|
||||
public Int16OperationHandler(byte[] codeBuffer, InstructionDecoder decoder, int length)
|
||||
: base(codeBuffer, decoder, length)
|
||||
public Int16OperationHandler(InstructionDecoder decoder)
|
||||
: base(decoder)
|
||||
{
|
||||
}
|
||||
|
||||
@ -121,30 +121,58 @@ public class Int16OperationHandler : InstructionHandler
|
||||
}
|
||||
|
||||
// Read the ModR/M byte
|
||||
var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
|
||||
var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
|
||||
|
||||
// Handle based on addressing mode
|
||||
if (mod != 3) // Memory operand
|
||||
{
|
||||
// Set the mnemonic based on the reg field
|
||||
instruction.Mnemonic = MemoryMnemonics[(int)reg];
|
||||
// Set the instruction type based on the reg field
|
||||
instruction.Type = MemoryInstructionTypes[(int)reg];
|
||||
|
||||
// Need to modify the default dword ptr to word ptr for 16-bit integers
|
||||
instruction.Operands = memOperand.Replace("dword ptr", "word ptr");
|
||||
// For memory operands, we need to set the size to 16-bit
|
||||
// Create a new memory operand with 16-bit size
|
||||
var int16Operand = memoryOperand;
|
||||
int16Operand.Size = 16;
|
||||
|
||||
// Set the structured operands
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
int16Operand
|
||||
];
|
||||
}
|
||||
else // Register operand (ST(i))
|
||||
{
|
||||
// Look up the register operation in our dictionary
|
||||
if (RegisterOperations.TryGetValue((reg, rm), out var operation))
|
||||
// Look up the instruction type in the register operations dictionary
|
||||
if (RegisterOperations.TryGetValue(((int)reg, (int)rm), out var operation))
|
||||
{
|
||||
instruction.Mnemonic = operation.Mnemonic;
|
||||
instruction.Operands = operation.Operands;
|
||||
instruction.Type = operation.Type;
|
||||
|
||||
// Create the FPU register operands
|
||||
var destOperand = OperandFactory.CreateFPURegisterOperand(operation.DestIndex);
|
||||
|
||||
// Set the structured operands
|
||||
if (operation.SrcIndex.HasValue)
|
||||
{
|
||||
var srcOperand = OperandFactory.CreateFPURegisterOperand(operation.SrcIndex.Value);
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
destOperand,
|
||||
srcOperand
|
||||
];
|
||||
}
|
||||
else
|
||||
{
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
destOperand
|
||||
];
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// Unknown instruction
|
||||
instruction.Mnemonic = "??";
|
||||
instruction.Operands = "";
|
||||
instruction.Type = InstructionType.Unknown;
|
||||
instruction.StructuredOperands = [];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1,3 +1,5 @@
|
||||
using X86Disassembler.X86.Operands;
|
||||
|
||||
namespace X86Disassembler.X86.Handlers.FloatingPoint;
|
||||
|
||||
/// <summary>
|
||||
@ -5,74 +7,72 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
|
||||
/// </summary>
|
||||
public class Int32OperationHandler : InstructionHandler
|
||||
{
|
||||
// Memory operand mnemonics for DA opcode - operations on int32
|
||||
private static readonly string[] MemoryMnemonics =
|
||||
// Memory operand instruction types for DA opcode - operations on int32
|
||||
private static readonly InstructionType[] MemoryInstructionTypes =
|
||||
[
|
||||
"fiadd", // 0
|
||||
"fimul", // 1
|
||||
"ficom", // 2
|
||||
"ficomp", // 3
|
||||
"fisub", // 4
|
||||
"fisubr", // 5
|
||||
"fidiv", // 6
|
||||
"fidivr" // 7
|
||||
InstructionType.Unknown, // fiadd - not in enum
|
||||
InstructionType.Unknown, // fimul - not in enum
|
||||
InstructionType.Unknown, // ficom - not in enum
|
||||
InstructionType.Unknown, // ficomp - not in enum
|
||||
InstructionType.Unknown, // fisub - not in enum
|
||||
InstructionType.Unknown, // fisubr - not in enum
|
||||
InstructionType.Unknown, // fidiv - not in enum
|
||||
InstructionType.Unknown // fidivr - not in enum
|
||||
];
|
||||
|
||||
// Register-register operations mapping (mod=3)
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex DestIndex, FpuRegisterIndex SrcIndex)> RegisterOperations = new()
|
||||
{
|
||||
// FCMOVB st(0), st(i)
|
||||
{ (RegisterIndex.A, RegisterIndex.A), ("fcmovb", "st(0), st(0)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), ("fcmovb", "st(0), st(1)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), ("fcmovb", "st(0), st(2)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), ("fcmovb", "st(0), st(3)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), ("fcmovb", "st(0), st(4)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), ("fcmovb", "st(0), st(5)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), ("fcmovb", "st(0), st(6)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), ("fcmovb", "st(0), st(7)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCMOVE st(0), st(i)
|
||||
{ (RegisterIndex.B, RegisterIndex.A), ("fcmove", "st(0), st(0)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.C), ("fcmove", "st(0), st(1)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.D), ("fcmove", "st(0), st(2)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.B), ("fcmove", "st(0), st(3)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.Sp), ("fcmove", "st(0), st(4)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.Bp), ("fcmove", "st(0), st(5)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.Si), ("fcmove", "st(0), st(6)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.Di), ("fcmove", "st(0), st(7)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.B, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.B, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.B, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCMOVBE st(0), st(i)
|
||||
{ (RegisterIndex.C, RegisterIndex.A), ("fcmovbe", "st(0), st(0)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.C), ("fcmovbe", "st(0), st(1)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.D), ("fcmovbe", "st(0), st(2)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.B), ("fcmovbe", "st(0), st(3)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.Sp), ("fcmovbe", "st(0), st(4)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.Bp), ("fcmovbe", "st(0), st(5)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.Si), ("fcmovbe", "st(0), st(6)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.Di), ("fcmovbe", "st(0), st(7)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.C, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.C, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.C, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCMOVU st(0), st(i)
|
||||
{ (RegisterIndex.D, RegisterIndex.A), ("fcmovu", "st(0), st(0)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.C), ("fcmovu", "st(0), st(1)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.D), ("fcmovu", "st(0), st(2)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.B), ("fcmovu", "st(0), st(3)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.Sp), ("fcmovu", "st(0), st(4)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.Bp), ("fcmovu", "st(0), st(5)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.Si), ("fcmovu", "st(0), st(6)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.Di), ("fcmovu", "st(0), st(7)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.D, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.D, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.D, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// Special case
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), ("fucompp", "") }
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) }
|
||||
};
|
||||
|
||||
/// <summary>
|
||||
/// Initializes a new instance of the Int32OperationHandler class
|
||||
/// </summary>
|
||||
/// <param name="codeBuffer">The buffer containing the code to decode</param>
|
||||
/// <param name="decoder">The instruction decoder that owns this handler</param>
|
||||
/// <param name="length">The length of the buffer</param>
|
||||
public Int32OperationHandler(byte[] codeBuffer, InstructionDecoder decoder, int length)
|
||||
: base(codeBuffer, decoder, length)
|
||||
public Int32OperationHandler(InstructionDecoder decoder)
|
||||
: base(decoder)
|
||||
{
|
||||
}
|
||||
|
||||
@ -100,30 +100,43 @@ public class Int32OperationHandler : InstructionHandler
|
||||
}
|
||||
|
||||
// Read the ModR/M byte
|
||||
var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
|
||||
var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
|
||||
|
||||
// Handle based on addressing mode
|
||||
if (mod != 3) // Memory operand
|
||||
{
|
||||
// Set the mnemonic based on the reg field
|
||||
instruction.Mnemonic = MemoryMnemonics[(int)reg];
|
||||
// Set the instruction type based on the reg field
|
||||
instruction.Type = MemoryInstructionTypes[(int)reg];
|
||||
|
||||
// Set the operands (already has dword ptr prefix for int32)
|
||||
instruction.Operands = memOperand;
|
||||
// Set the structured operands
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
memoryOperand
|
||||
];
|
||||
}
|
||||
else // Register operand (ST(i))
|
||||
{
|
||||
// Look up the register operation in our dictionary
|
||||
// Look up the instruction type in the register operations dictionary
|
||||
if (RegisterOperations.TryGetValue((reg, rm), out var operation))
|
||||
{
|
||||
instruction.Mnemonic = operation.Mnemonic;
|
||||
instruction.Operands = operation.Operands;
|
||||
instruction.Type = operation.Type;
|
||||
|
||||
// Create the FPU register operands
|
||||
var destOperand = OperandFactory.CreateFPURegisterOperand(operation.DestIndex);
|
||||
var srcOperand = OperandFactory.CreateFPURegisterOperand(operation.SrcIndex);
|
||||
|
||||
// Set the structured operands
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
destOperand,
|
||||
srcOperand
|
||||
];
|
||||
}
|
||||
else
|
||||
{
|
||||
// Unknown instruction
|
||||
instruction.Mnemonic = "??";
|
||||
instruction.Operands = "";
|
||||
instruction.Type = InstructionType.Unknown;
|
||||
instruction.StructuredOperands = [];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1,3 +1,5 @@
|
||||
using X86Disassembler.X86.Operands;
|
||||
|
||||
namespace X86Disassembler.X86.Handlers.FloatingPoint;
|
||||
|
||||
/// <summary>
|
||||
@ -5,81 +7,79 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
|
||||
/// </summary>
|
||||
public class LoadStoreControlHandler : InstructionHandler
|
||||
{
|
||||
// Memory operand mnemonics for D9 opcode - load, store, and control operations
|
||||
private static readonly string[] MemoryMnemonics =
|
||||
// Memory operand instruction types for D9 opcode - load, store, and control operations
|
||||
private static readonly InstructionType[] MemoryInstructionTypes =
|
||||
[
|
||||
"fld", // 0
|
||||
"??", // 1
|
||||
"fst", // 2
|
||||
"fstp", // 3
|
||||
"fldenv", // 4
|
||||
"fldcw", // 5
|
||||
"fnstenv", // 6
|
||||
"fnstcw" // 7
|
||||
InstructionType.Fld, // 0
|
||||
InstructionType.Unknown, // 1
|
||||
InstructionType.Fst, // 2
|
||||
InstructionType.Fstp, // 3
|
||||
InstructionType.Unknown, // 4 - fldenv not in enum
|
||||
InstructionType.Fldcw, // 5
|
||||
InstructionType.Unknown, // 6 - fnstenv not in enum
|
||||
InstructionType.Fnstcw // 7
|
||||
];
|
||||
|
||||
// Register-register operations mapping (mod=3)
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex? OperandIndex)> RegisterOperations = new()
|
||||
{
|
||||
// FLD ST(i)
|
||||
{ (RegisterIndex.A, RegisterIndex.A), ("fld", "st(0)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), ("fld", "st(1)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), ("fld", "st(2)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), ("fld", "st(3)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), ("fld", "st(4)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), ("fld", "st(5)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), ("fld", "st(6)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), ("fld", "st(7)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Fld, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Fld, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Fld, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Fld, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Fld, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Fld, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Fld, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Fld, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FXCH ST(i)
|
||||
{ (RegisterIndex.B, RegisterIndex.A), ("fxch", "st(0)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.C), ("fxch", "st(1)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.D), ("fxch", "st(2)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.B), ("fxch", "st(3)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.Sp), ("fxch", "st(4)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.Bp), ("fxch", "st(5)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.Si), ("fxch", "st(6)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.Di), ("fxch", "st(7)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.A), (InstructionType.Fxch, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.B, RegisterIndex.C), (InstructionType.Fxch, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.B, RegisterIndex.D), (InstructionType.Fxch, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.B, RegisterIndex.B), (InstructionType.Fxch, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Sp), (InstructionType.Fxch, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Bp), (InstructionType.Fxch, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Si), (InstructionType.Fxch, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Di), (InstructionType.Fxch, FpuRegisterIndex.ST7) },
|
||||
|
||||
// D9E0-D9EF special instructions (reg=6)
|
||||
{ (RegisterIndex.Si, RegisterIndex.A), ("fchs", "") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.B), ("fabs", "") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Si), ("ftst", "") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Di), ("fxam", "") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.A), (InstructionType.Fchs, null) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.B), (InstructionType.Fabs, null) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Si), (InstructionType.Ftst, null) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Di), (InstructionType.Fxam, null) },
|
||||
|
||||
// D9F0-D9FF special instructions (reg=7)
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), ("f2xm1", "") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), ("fyl2x", "") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), ("fptan", "") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), ("fpatan", "") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), ("fxtract", "") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), ("fprem1", "") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), ("fdecstp", "") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), ("fincstp", "") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Unknown, null) }, // f2xm1 not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, null) }, // fyl2x not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Unknown, null) }, // fptan not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Unknown, null) }, // fpatan not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Unknown, null) }, // fxtract not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Unknown, null) }, // fprem1 not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Unknown, null) }, // fdecstp not in enum
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Unknown, null) }, // fincstp not in enum
|
||||
|
||||
// D9D0-D9DF special instructions (reg=5)
|
||||
{ (RegisterIndex.Sp, RegisterIndex.A), ("fprem", "") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.B), ("fyl2xp1", "") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.C), ("fsqrt", "") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.D), ("fsincos", "") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Si), ("frndint", "") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Di), ("fscale", "") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Sp), ("fsin", "") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Bp), ("fcos", "") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.A), (InstructionType.Unknown, null) }, // fprem not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.B), (InstructionType.Unknown, null) }, // fyl2xp1 not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.C), (InstructionType.Unknown, null) }, // fsqrt not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.D), (InstructionType.Unknown, null) }, // fsincos not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Si), (InstructionType.Unknown, null) }, // frndint not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Di), (InstructionType.Unknown, null) }, // fscale not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Sp), (InstructionType.Unknown, null) }, // fsin not in enum
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Bp), (InstructionType.Unknown, null) }, // fcos not in enum
|
||||
|
||||
// D9C8-D9CF special instructions (reg=4)
|
||||
{ (RegisterIndex.Bp, RegisterIndex.A), ("fnop", "") },
|
||||
{ (RegisterIndex.Bp, RegisterIndex.C), ("fwait", "") }
|
||||
{ (RegisterIndex.Bp, RegisterIndex.A), (InstructionType.Unknown, null) }, // fnop not in enum
|
||||
{ (RegisterIndex.Bp, RegisterIndex.C), (InstructionType.Unknown, null) } // fwait not in enum
|
||||
};
|
||||
|
||||
|
||||
/// <summary>
|
||||
/// Initializes a new instance of the LoadStoreControlHandler class
|
||||
/// </summary>
|
||||
/// <param name="codeBuffer">The buffer containing the code to decode</param>
|
||||
/// <param name="decoder">The instruction decoder that owns this handler</param>
|
||||
/// <param name="length">The length of the buffer</param>
|
||||
public LoadStoreControlHandler(byte[] codeBuffer, InstructionDecoder decoder, int length)
|
||||
: base(codeBuffer, decoder, length)
|
||||
public LoadStoreControlHandler(InstructionDecoder decoder)
|
||||
: base(decoder)
|
||||
{
|
||||
}
|
||||
|
||||
@ -107,46 +107,59 @@ public class LoadStoreControlHandler : InstructionHandler
|
||||
}
|
||||
|
||||
// Read the ModR/M byte
|
||||
var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
|
||||
var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
|
||||
|
||||
// Handle based on addressing mode
|
||||
if (mod != 3) // Memory operand
|
||||
{
|
||||
// Set the mnemonic based on the reg field
|
||||
instruction.Mnemonic = MemoryMnemonics[(int)reg];
|
||||
// Set the instruction type based on the reg field
|
||||
instruction.Type = MemoryInstructionTypes[(int)reg];
|
||||
|
||||
// Different operand types based on the instruction
|
||||
// Set the size based on the operation
|
||||
if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fld, fst, fstp
|
||||
{
|
||||
// Keep the dword ptr prefix from ModRMDecoder
|
||||
instruction.Operands = memOperand;
|
||||
// Keep the default 32-bit size for floating point operations
|
||||
memoryOperand.Size = 32;
|
||||
}
|
||||
else // fldenv, fldcw, fnstenv, fnstcw
|
||||
else if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // fldcw, fnstcw
|
||||
{
|
||||
if (reg == RegisterIndex.Di) // fldcw - should use word ptr
|
||||
{
|
||||
instruction.Operands = memOperand.Replace("dword ptr", "word ptr");
|
||||
}
|
||||
else // fldenv, fnstenv, fnstcw
|
||||
{
|
||||
// Remove the dword ptr prefix for other control operations
|
||||
instruction.Operands = memOperand.Replace("dword ptr ", "");
|
||||
}
|
||||
// Set to 16-bit for control word operations
|
||||
memoryOperand.Size = 16;
|
||||
}
|
||||
|
||||
// Set the structured operands
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
memoryOperand
|
||||
];
|
||||
}
|
||||
else // Register operand (ST(i))
|
||||
{
|
||||
// Look up the register operation in our dictionary
|
||||
// Look up the instruction type in the register operations dictionary
|
||||
if (RegisterOperations.TryGetValue((reg, rm), out var operation))
|
||||
{
|
||||
instruction.Mnemonic = operation.Mnemonic;
|
||||
instruction.Operands = operation.Operands;
|
||||
instruction.Type = operation.Type;
|
||||
|
||||
// Set the structured operands
|
||||
if (operation.OperandIndex.HasValue)
|
||||
{
|
||||
var operand = OperandFactory.CreateFPURegisterOperand(operation.OperandIndex.Value);
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
operand
|
||||
];
|
||||
}
|
||||
else
|
||||
{
|
||||
// No operands for instructions like fchs, fabs, etc.
|
||||
instruction.StructuredOperands = [];
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// Unknown instruction
|
||||
instruction.Mnemonic = "??";
|
||||
instruction.Operands = "";
|
||||
instruction.Type = InstructionType.Unknown;
|
||||
instruction.StructuredOperands = [];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1,3 +1,5 @@
|
||||
using X86Disassembler.X86.Operands;
|
||||
|
||||
namespace X86Disassembler.X86.Handlers.FloatingPoint;
|
||||
|
||||
/// <summary>
|
||||
@ -18,68 +20,79 @@ public class LoadStoreFloat64Handler : InstructionHandler
|
||||
"fnstsw" // 7
|
||||
];
|
||||
|
||||
// Memory operand instruction types for DD opcode
|
||||
private static readonly InstructionType[] MemoryInstructionTypes =
|
||||
[
|
||||
InstructionType.Fld, // 0
|
||||
InstructionType.Unknown, // 1
|
||||
InstructionType.Fst, // 2
|
||||
InstructionType.Fstp, // 3
|
||||
InstructionType.Unknown, // 4 - frstor not in enum
|
||||
InstructionType.Unknown, // 5
|
||||
InstructionType.Unknown, // 6 - fnsave not in enum
|
||||
InstructionType.Fnstsw // 7
|
||||
];
|
||||
|
||||
// Register-register operations mapping (mod=3)
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex OperandIndex)> RegisterOperations = new()
|
||||
{
|
||||
// FFREE ST(i)
|
||||
{ (RegisterIndex.A, RegisterIndex.A), ("ffree", "st(0)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), ("ffree", "st(1)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), ("ffree", "st(2)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), ("ffree", "st(3)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), ("ffree", "st(4)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), ("ffree", "st(5)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), ("ffree", "st(6)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), ("ffree", "st(7)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FST ST(i)
|
||||
{ (RegisterIndex.C, RegisterIndex.A), ("fst", "st(0)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.C), ("fst", "st(1)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.D), ("fst", "st(2)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.B), ("fst", "st(3)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.Sp), ("fst", "st(4)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.Bp), ("fst", "st(5)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.Si), ("fst", "st(6)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.Di), ("fst", "st(7)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Fst, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.C, RegisterIndex.C), (InstructionType.Fst, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.C, RegisterIndex.D), (InstructionType.Fst, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.C, RegisterIndex.B), (InstructionType.Fst, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Sp), (InstructionType.Fst, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Bp), (InstructionType.Fst, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Si), (InstructionType.Fst, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Di), (InstructionType.Fst, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FSTP ST(i)
|
||||
{ (RegisterIndex.D, RegisterIndex.A), ("fstp", "st(0)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.C), ("fstp", "st(1)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.D), ("fstp", "st(2)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.B), ("fstp", "st(3)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.Sp), ("fstp", "st(4)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.Bp), ("fstp", "st(5)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.Si), ("fstp", "st(6)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.Di), ("fstp", "st(7)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.A), (InstructionType.Fstp, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.D, RegisterIndex.C), (InstructionType.Fstp, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.D, RegisterIndex.D), (InstructionType.Fstp, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.D, RegisterIndex.B), (InstructionType.Fstp, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Sp), (InstructionType.Fstp, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Bp), (InstructionType.Fstp, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Si), (InstructionType.Fstp, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Di), (InstructionType.Fstp, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FUCOM ST(i)
|
||||
{ (RegisterIndex.Si, RegisterIndex.A), ("fucom", "st(0)") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.C), ("fucom", "st(1)") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.D), ("fucom", "st(2)") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.B), ("fucom", "st(3)") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Sp), ("fucom", "st(4)") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Bp), ("fucom", "st(5)") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Si), ("fucom", "st(6)") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Di), ("fucom", "st(7)") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Si, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FUCOMP ST(i)
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), ("fucomp", "st(0)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), ("fucomp", "st(1)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), ("fucomp", "st(2)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), ("fucomp", "st(3)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), ("fucomp", "st(4)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), ("fucomp", "st(5)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), ("fucomp", "st(6)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), ("fucomp", "st(7)") }
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST7) }
|
||||
};
|
||||
|
||||
/// <summary>
|
||||
/// Initializes a new instance of the LoadStoreFloat64Handler class
|
||||
/// </summary>
|
||||
/// <param name="codeBuffer">The buffer containing the code to decode</param>
|
||||
/// <param name="decoder">The instruction decoder that owns this handler</param>
|
||||
/// <param name="length">The length of the buffer</param>
|
||||
public LoadStoreFloat64Handler(byte[] codeBuffer, InstructionDecoder decoder, int length)
|
||||
: base(codeBuffer, decoder, length)
|
||||
public LoadStoreFloat64Handler(InstructionDecoder decoder)
|
||||
: base(decoder)
|
||||
{
|
||||
}
|
||||
|
||||
@ -94,54 +107,75 @@ public class LoadStoreFloat64Handler : InstructionHandler
|
||||
}
|
||||
|
||||
/// <summary>
|
||||
/// Decodes a floating-point instruction for load/store float64 operations
|
||||
/// Decodes a floating point instruction with the DD opcode
|
||||
/// </summary>
|
||||
/// <param name="opcode">The opcode of the instruction</param>
|
||||
/// <param name="instruction">The instruction object to populate</param>
|
||||
/// <returns>True if the instruction was successfully decoded</returns>
|
||||
public override bool Decode(byte opcode, Instruction instruction)
|
||||
{
|
||||
// Check if we have enough bytes for the ModR/M byte
|
||||
if (!Decoder.CanReadByte())
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
// Read the ModR/M byte
|
||||
var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM(true); // true for 64-bit operand
|
||||
var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
|
||||
|
||||
// Handle based on addressing mode
|
||||
// Set the instruction type based on the mod and reg fields
|
||||
if (mod != 3) // Memory operand
|
||||
{
|
||||
// Set the mnemonic based on the reg field
|
||||
instruction.Mnemonic = MemoryMnemonics[(int)reg];
|
||||
instruction.Type = MemoryInstructionTypes[(int)reg];
|
||||
|
||||
if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // fld, fst, fstp
|
||||
// For memory operands, the instruction depends on the reg field
|
||||
switch (reg)
|
||||
{
|
||||
// Keep the qword ptr prefix from ModRMDecoder
|
||||
instruction.Operands = memOperand;
|
||||
}
|
||||
else // frstor, fnsave, fnstsw
|
||||
{
|
||||
// Remove the qword ptr prefix for these operations
|
||||
instruction.Operands = memOperand.Replace("qword ptr ", "");
|
||||
case RegisterIndex.A: // FLD m64real
|
||||
// Set the structured operands
|
||||
memoryOperand.Size = 64; // Set size to 64 bits for double precision
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
memoryOperand
|
||||
];
|
||||
return true;
|
||||
|
||||
case RegisterIndex.C: // FST m64real
|
||||
case RegisterIndex.D: // FSTP m64real
|
||||
// Set the structured operands
|
||||
memoryOperand.Size = 64; // Set size to 64 bits for double precision
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
memoryOperand
|
||||
];
|
||||
return true;
|
||||
|
||||
default:
|
||||
// For unsupported instructions, just set the type to Unknown
|
||||
instruction.Type = InstructionType.Unknown;
|
||||
return true;
|
||||
}
|
||||
}
|
||||
else // Register operand (ST(i))
|
||||
else // Register operand (mod == 3)
|
||||
{
|
||||
// Look up the register operation in our dictionary
|
||||
// Look up the instruction type in the register operations dictionary
|
||||
if (RegisterOperations.TryGetValue((reg, rm), out var operation))
|
||||
{
|
||||
instruction.Mnemonic = operation.Mnemonic;
|
||||
instruction.Operands = operation.Operands;
|
||||
}
|
||||
else
|
||||
{
|
||||
// Unknown instruction
|
||||
instruction.Mnemonic = "??";
|
||||
instruction.Operands = "";
|
||||
instruction.Type = operation.Type;
|
||||
|
||||
// Create the FPU register operand
|
||||
var fpuRegisterOperand = OperandFactory.CreateFPURegisterOperand(operation.OperandIndex);
|
||||
|
||||
// Set the structured operands
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
fpuRegisterOperand
|
||||
];
|
||||
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
return false;
|
||||
}
|
||||
}
|
||||
@ -1,3 +1,5 @@
|
||||
using X86Disassembler.X86.Operands;
|
||||
|
||||
namespace X86Disassembler.X86.Handlers.FloatingPoint;
|
||||
|
||||
/// <summary>
|
||||
@ -5,66 +7,64 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
|
||||
/// </summary>
|
||||
public class LoadStoreInt16Handler : InstructionHandler
|
||||
{
|
||||
// Memory operand mnemonics for DF opcode - load/store int16, misc
|
||||
private static readonly string[] MemoryMnemonics =
|
||||
// Memory operand instruction types for DF opcode - load/store int16, misc
|
||||
private static readonly InstructionType[] MemoryInstructionTypes =
|
||||
[
|
||||
"fild", // 0 - 16-bit integer
|
||||
"??", // 1
|
||||
"fist", // 2 - 16-bit integer
|
||||
"fistp", // 3 - 16-bit integer
|
||||
"fbld", // 4 - 80-bit packed BCD
|
||||
"fild", // 5 - 64-bit integer
|
||||
"fbstp", // 6 - 80-bit packed BCD
|
||||
"fistp" // 7 - 64-bit integer
|
||||
InstructionType.Unknown, // fild - not in enum
|
||||
InstructionType.Unknown, // ??
|
||||
InstructionType.Unknown, // fist - not in enum
|
||||
InstructionType.Unknown, // fistp - not in enum
|
||||
InstructionType.Unknown, // fbld - not in enum
|
||||
InstructionType.Unknown, // fild - 64-bit integer - not in enum
|
||||
InstructionType.Unknown, // fbstp - not in enum
|
||||
InstructionType.Unknown // fistp - 64-bit integer - not in enum
|
||||
];
|
||||
|
||||
// Register-register operations mapping (mod=3)
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex OperandIndex, FpuRegisterIndex? SrcIndex)> RegisterOperations = new()
|
||||
{
|
||||
// FFREEP ST(i)
|
||||
{ (RegisterIndex.A, RegisterIndex.A), ("ffreep", "st(0)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), ("ffreep", "st(1)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), ("ffreep", "st(2)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), ("ffreep", "st(3)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), ("ffreep", "st(4)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), ("ffreep", "st(5)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), ("ffreep", "st(6)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), ("ffreep", "st(7)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, null) },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST1, null) },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST2, null) },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST3, null) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST4, null) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST5, null) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST6, null) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST7, null) },
|
||||
|
||||
// Special cases
|
||||
{ (RegisterIndex.B, RegisterIndex.A), ("fxch", "") },
|
||||
{ (RegisterIndex.C, RegisterIndex.A), ("fstp", "st(1)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.A), ("fstp", "st(1)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.A), (InstructionType.Fxch, FpuRegisterIndex.ST0, null) },
|
||||
{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Fstp, FpuRegisterIndex.ST1, null) },
|
||||
{ (RegisterIndex.D, RegisterIndex.A), (InstructionType.Fstp, FpuRegisterIndex.ST1, null) },
|
||||
|
||||
// FUCOMIP ST(0), ST(i)
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), ("fucomip", "st(0), st(0)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), ("fucomip", "st(0), st(1)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), ("fucomip", "st(0), st(2)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), ("fucomip", "st(0), st(3)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), ("fucomip", "st(0), st(4)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), ("fucomip", "st(0), st(5)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), ("fucomip", "st(0), st(6)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), ("fucomip", "st(0), st(7)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCOMIP ST(0), ST(i)
|
||||
{ (RegisterIndex.Sp, RegisterIndex.A), ("fcomip", "st(0), st(0)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.C), ("fcomip", "st(0), st(1)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.D), ("fcomip", "st(0), st(2)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.B), ("fcomip", "st(0), st(3)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Sp), ("fcomip", "st(0), st(4)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Bp), ("fcomip", "st(0), st(5)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Si), ("fcomip", "st(0), st(6)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Di), ("fcomip", "st(0), st(7)") }
|
||||
{ (RegisterIndex.Sp, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) }
|
||||
};
|
||||
|
||||
/// <summary>
|
||||
/// Initializes a new instance of the LoadStoreInt16Handler class
|
||||
/// </summary>
|
||||
/// <param name="codeBuffer">The buffer containing the code to decode</param>
|
||||
/// <param name="decoder">The instruction decoder that owns this handler</param>
|
||||
/// <param name="length">The length of the buffer</param>
|
||||
public LoadStoreInt16Handler(byte[] codeBuffer, InstructionDecoder decoder, int length)
|
||||
: base(codeBuffer, decoder, length)
|
||||
public LoadStoreInt16Handler(InstructionDecoder decoder)
|
||||
: base(decoder)
|
||||
{
|
||||
}
|
||||
|
||||
@ -92,7 +92,7 @@ public class LoadStoreInt16Handler : InstructionHandler
|
||||
}
|
||||
|
||||
// Read the ModR/M byte
|
||||
var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
|
||||
var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
|
||||
|
||||
// Check for FNSTSW AX (DF E0)
|
||||
if (mod == 3 && reg == RegisterIndex.Bp && rm == RegisterIndex.A)
|
||||
@ -104,43 +104,65 @@ public class LoadStoreInt16Handler : InstructionHandler
|
||||
// Handle based on addressing mode
|
||||
if (mod != 3) // Memory operand
|
||||
{
|
||||
// Set the mnemonic based on the reg field
|
||||
instruction.Mnemonic = MemoryMnemonics[(int)reg];
|
||||
// Set the instruction type based on the reg field
|
||||
instruction.Type = MemoryInstructionTypes[(int)reg];
|
||||
|
||||
// Get the base operand without size prefix
|
||||
string baseOperand = memOperand.Replace("dword ptr ", "");
|
||||
|
||||
// Apply the appropriate size prefix based on the operation
|
||||
// Set the size based on the operation
|
||||
if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // 16-bit integer operations
|
||||
{
|
||||
instruction.Operands = $"word ptr {baseOperand}";
|
||||
// Set to 16-bit for integer operations
|
||||
memoryOperand.Size = 16;
|
||||
}
|
||||
else if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // 64-bit integer operations
|
||||
{
|
||||
instruction.Operands = $"qword ptr {baseOperand}";
|
||||
// Set to 64-bit for integer operations
|
||||
memoryOperand.Size = 64;
|
||||
}
|
||||
else if (reg == RegisterIndex.Si || reg == RegisterIndex.Sp) // 80-bit packed BCD operations
|
||||
{
|
||||
instruction.Operands = $"tbyte ptr {baseOperand}";
|
||||
}
|
||||
else // Other operations
|
||||
{
|
||||
instruction.Operands = memOperand;
|
||||
// Set to 80-bit for BCD operations
|
||||
memoryOperand.Size = 80;
|
||||
}
|
||||
|
||||
// Set the structured operands
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
memoryOperand
|
||||
];
|
||||
}
|
||||
else // Register operand (ST(i))
|
||||
{
|
||||
// Look up the register operation in our dictionary
|
||||
// Look up the instruction type in the register operations dictionary
|
||||
if (RegisterOperations.TryGetValue((reg, rm), out var operation))
|
||||
{
|
||||
instruction.Mnemonic = operation.Mnemonic;
|
||||
instruction.Operands = operation.Operands;
|
||||
instruction.Type = operation.Type;
|
||||
|
||||
// Create the FPU register operands
|
||||
var destOperand = OperandFactory.CreateFPURegisterOperand(operation.OperandIndex);
|
||||
|
||||
// Set the structured operands
|
||||
if (operation.SrcIndex.HasValue)
|
||||
{
|
||||
var srcOperand = OperandFactory.CreateFPURegisterOperand(operation.SrcIndex.Value);
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
destOperand,
|
||||
srcOperand
|
||||
];
|
||||
}
|
||||
else
|
||||
{
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
destOperand
|
||||
];
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// Unknown instruction
|
||||
instruction.Mnemonic = "??";
|
||||
instruction.Operands = "";
|
||||
instruction.Type = InstructionType.Unknown;
|
||||
instruction.StructuredOperands = [];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -1,3 +1,5 @@
|
||||
using X86Disassembler.X86.Operands;
|
||||
|
||||
namespace X86Disassembler.X86.Handlers.FloatingPoint;
|
||||
|
||||
/// <summary>
|
||||
@ -5,95 +7,93 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint;
|
||||
/// </summary>
|
||||
public class LoadStoreInt32Handler : InstructionHandler
|
||||
{
|
||||
// Memory operand mnemonics for DB opcode - load/store int32, misc
|
||||
private static readonly string[] MemoryMnemonics =
|
||||
// Memory operand instruction types for DB opcode - load/store int32, misc
|
||||
private static readonly InstructionType[] MemoryInstructionTypes =
|
||||
[
|
||||
"fild", // 0 - 32-bit integer
|
||||
"??", // 1
|
||||
"fist", // 2 - 32-bit integer
|
||||
"fistp", // 3 - 32-bit integer
|
||||
"??", // 4
|
||||
"fld", // 5 - 80-bit extended precision
|
||||
"??", // 6
|
||||
"fstp" // 7 - 80-bit extended precision
|
||||
InstructionType.Unknown, // fild - not in enum
|
||||
InstructionType.Unknown, // ??
|
||||
InstructionType.Unknown, // fist - not in enum
|
||||
InstructionType.Unknown, // fistp - not in enum
|
||||
InstructionType.Unknown, // ??
|
||||
InstructionType.Fld, // fld - 80-bit extended precision
|
||||
InstructionType.Unknown, // ??
|
||||
InstructionType.Fstp // fstp - 80-bit extended precision
|
||||
];
|
||||
|
||||
// Register-register operations mapping (mod=3)
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (string Mnemonic, string Operands)> RegisterOperations = new()
|
||||
private static readonly Dictionary<(RegisterIndex Reg, RegisterIndex Rm), (InstructionType Type, FpuRegisterIndex DestIndex, FpuRegisterIndex? SrcIndex)> RegisterOperations = new()
|
||||
{
|
||||
// FCMOVNB ST(0), ST(i)
|
||||
{ (RegisterIndex.A, RegisterIndex.A), ("fcmovnb", "st(0), st(0)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), ("fcmovnb", "st(0), st(1)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), ("fcmovnb", "st(0), st(2)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), ("fcmovnb", "st(0), st(3)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), ("fcmovnb", "st(0), st(4)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), ("fcmovnb", "st(0), st(5)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), ("fcmovnb", "st(0), st(6)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), ("fcmovnb", "st(0), st(7)") },
|
||||
{ (RegisterIndex.A, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.A, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.A, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.A, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.A, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCMOVNE ST(0), ST(i)
|
||||
{ (RegisterIndex.B, RegisterIndex.A), ("fcmovne", "st(0), st(0)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.C), ("fcmovne", "st(0), st(1)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.D), ("fcmovne", "st(0), st(2)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.B), ("fcmovne", "st(0), st(3)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.Sp), ("fcmovne", "st(0), st(4)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.Bp), ("fcmovne", "st(0), st(5)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.Si), ("fcmovne", "st(0), st(6)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.Di), ("fcmovne", "st(0), st(7)") },
|
||||
{ (RegisterIndex.B, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.B, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.B, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.B, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.B, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCMOVNBE ST(0), ST(i)
|
||||
{ (RegisterIndex.C, RegisterIndex.A), ("fcmovnbe", "st(0), st(0)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.C), ("fcmovnbe", "st(0), st(1)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.D), ("fcmovnbe", "st(0), st(2)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.B), ("fcmovnbe", "st(0), st(3)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.Sp), ("fcmovnbe", "st(0), st(4)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.Bp), ("fcmovnbe", "st(0), st(5)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.Si), ("fcmovnbe", "st(0), st(6)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.Di), ("fcmovnbe", "st(0), st(7)") },
|
||||
{ (RegisterIndex.C, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.C, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.C, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.C, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.C, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCMOVNU ST(0), ST(i)
|
||||
{ (RegisterIndex.D, RegisterIndex.A), ("fcmovnu", "st(0), st(0)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.C), ("fcmovnu", "st(0), st(1)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.D), ("fcmovnu", "st(0), st(2)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.B), ("fcmovnu", "st(0), st(3)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.Sp), ("fcmovnu", "st(0), st(4)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.Bp), ("fcmovnu", "st(0), st(5)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.Si), ("fcmovnu", "st(0), st(6)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.Di), ("fcmovnu", "st(0), st(7)") },
|
||||
{ (RegisterIndex.D, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.D, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.D, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.D, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.D, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// Special cases
|
||||
{ (RegisterIndex.Si, RegisterIndex.C), ("fclex", "") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.D), ("finit", "") },
|
||||
{ (RegisterIndex.Si, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, null) }, // fclex
|
||||
{ (RegisterIndex.Si, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, null) }, // finit
|
||||
|
||||
// FUCOMI ST(0), ST(i)
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), ("fucomi", "st(0), st(0)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), ("fucomi", "st(0), st(1)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), ("fucomi", "st(0), st(2)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), ("fucomi", "st(0), st(3)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), ("fucomi", "st(0), st(4)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), ("fucomi", "st(0), st(5)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), ("fucomi", "st(0), st(6)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), ("fucomi", "st(0), st(7)") },
|
||||
{ (RegisterIndex.Di, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Di, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) },
|
||||
|
||||
// FCOMI ST(0), ST(i)
|
||||
{ (RegisterIndex.Sp, RegisterIndex.A), ("fcomi", "st(0), st(0)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.C), ("fcomi", "st(0), st(1)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.D), ("fcomi", "st(0), st(2)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.B), ("fcomi", "st(0), st(3)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Sp), ("fcomi", "st(0), st(4)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Bp), ("fcomi", "st(0), st(5)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Si), ("fcomi", "st(0), st(6)") },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Di), ("fcomi", "st(0), st(7)") }
|
||||
{ (RegisterIndex.Sp, RegisterIndex.A), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST0) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.C), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST1) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.D), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST2) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.B), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST3) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Sp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST4) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Bp), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST5) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Si), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST6) },
|
||||
{ (RegisterIndex.Sp, RegisterIndex.Di), (InstructionType.Unknown, FpuRegisterIndex.ST0, FpuRegisterIndex.ST7) }
|
||||
};
|
||||
|
||||
/// <summary>
|
||||
/// Initializes a new instance of the LoadStoreInt32Handler class
|
||||
/// </summary>
|
||||
/// <param name="codeBuffer">The buffer containing the code to decode</param>
|
||||
/// <param name="decoder">The instruction decoder that owns this handler</param>
|
||||
/// <param name="length">The length of the buffer</param>
|
||||
public LoadStoreInt32Handler(byte[] codeBuffer, InstructionDecoder decoder, int length)
|
||||
: base(codeBuffer, decoder, length)
|
||||
public LoadStoreInt32Handler(InstructionDecoder decoder)
|
||||
: base(decoder)
|
||||
{
|
||||
}
|
||||
|
||||
@ -121,45 +121,65 @@ public class LoadStoreInt32Handler : InstructionHandler
|
||||
}
|
||||
|
||||
// Read the ModR/M byte
|
||||
var (mod, reg, rm, memOperand) = ModRMDecoder.ReadModRM();
|
||||
var (mod, reg, rm, memoryOperand) = ModRMDecoder.ReadModRM();
|
||||
|
||||
// Handle based on addressing mode
|
||||
if (mod != 3) // Memory operand
|
||||
{
|
||||
// Set the mnemonic based on the reg field
|
||||
instruction.Mnemonic = MemoryMnemonics[(int)reg];
|
||||
// Set the instruction type based on the reg field
|
||||
instruction.Type = MemoryInstructionTypes[(int)reg];
|
||||
|
||||
// Get the base operand without size prefix
|
||||
string baseOperand = memOperand.Replace("dword ptr ", "");
|
||||
|
||||
// Apply the appropriate size prefix based on the operation
|
||||
// Set the size based on the operation
|
||||
if (reg == RegisterIndex.A || reg == RegisterIndex.C || reg == RegisterIndex.D) // 32-bit integer operations
|
||||
{
|
||||
// Keep the dword ptr prefix for integer operations
|
||||
instruction.Operands = memOperand;
|
||||
// Keep the default 32-bit size
|
||||
memoryOperand.Size = 32;
|
||||
}
|
||||
else if (reg == RegisterIndex.Di || reg == RegisterIndex.Bp) // 80-bit extended precision operations
|
||||
{
|
||||
instruction.Operands = $"tword ptr {baseOperand}";
|
||||
}
|
||||
else
|
||||
{
|
||||
instruction.Operands = memOperand;
|
||||
// Set to 80-bit for extended precision
|
||||
memoryOperand.Size = 80;
|
||||
}
|
||||
|
||||
// Set the structured operands
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
memoryOperand
|
||||
];
|
||||
}
|
||||
else // Register operand (ST(i))
|
||||
{
|
||||
// Look up the register operation in our dictionary
|
||||
// Look up the instruction type in the register operations dictionary
|
||||
if (RegisterOperations.TryGetValue((reg, rm), out var operation))
|
||||
{
|
||||
instruction.Mnemonic = operation.Mnemonic;
|
||||
instruction.Operands = operation.Operands;
|
||||
instruction.Type = operation.Type;
|
||||
|
||||
// Create the FPU register operands
|
||||
var destOperand = OperandFactory.CreateFPURegisterOperand(operation.DestIndex);
|
||||
|
||||
// Set the structured operands
|
||||
if (operation.SrcIndex.HasValue)
|
||||
{
|
||||
var srcOperand = OperandFactory.CreateFPURegisterOperand(operation.SrcIndex.Value);
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
destOperand,
|
||||
srcOperand
|
||||
];
|
||||
}
|
||||
else
|
||||
{
|
||||
instruction.StructuredOperands =
|
||||
[
|
||||
destOperand
|
||||
];
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// Unknown instruction
|
||||
instruction.Mnemonic = "??";
|
||||
instruction.Operands = "";
|
||||
instruction.Type = InstructionType.Unknown;
|
||||
instruction.StructuredOperands = [];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user