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Code Issues Releases Activity

fixes to FPU tests

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This commit is contained in:
bird_egop 2025-04-18 13:47:34 +03:00
parent 8567cf1d6d
commit d089fc9b28
4 changed files with 8 additions and 9 deletions
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2
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FdivpStiStHandler.cs
View File

@ -8,7 +8,7 @@ using X86Disassembler.X86.Operands;
public class FdivpStiStHandler : InstructionHandler
{
/// <summary>
/// Initializes a new instance of the FdivrpStiStHandler class
/// Initializes a new instance of the FdivpStiStHandler class
/// </summary>
/// <param name="decoder">The instruction decoder that owns this handler</param>
public FdivpStiStHandler(InstructionDecoder decoder)

8
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FsubStiStHandler.cs
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@ -3,7 +3,7 @@ namespace X86Disassembler.X86.Handlers.FloatingPoint.Arithmetic;
using X86Disassembler.X86.Operands;
/// <summary>
/// Handler for FSUB ST(i), ST instruction (DC E0-E7)
/// Handler for FSUBR ST(i), ST instruction (DC E0-E7)
/// </summary>
public class FsubStiStHandler : InstructionHandler
{
@ -23,7 +23,7 @@ public class FsubStiStHandler : InstructionHandler
/// <returns>True if this handler can decode the opcode</returns>
public override bool CanHandle(byte opcode)
{
// FSUB ST(i), ST is DC E0-E7
// FSUBR ST(i), ST is DC E0-E7
if (opcode != 0xDC) return false;
if (!Decoder.CanReadByte())
@ -39,7 +39,7 @@ public class FsubStiStHandler : InstructionHandler
}
/// <summary>
/// Decodes a FSUB ST(i), ST instruction
/// Decodes a FSUBR ST(i), ST instruction
/// </summary>
/// <param name="opcode">The opcode of the instruction</param>
/// <param name="instruction">The instruction object to populate</param>
@ -55,7 +55,7 @@ public class FsubStiStHandler : InstructionHandler
var stIndex = (FpuRegisterIndex)(Decoder.ReadByte() - 0xE0);
// Set the instruction type
instruction.Type = InstructionType.Fsub;
instruction.Type = InstructionType.Fsubr;
// Create the FPU register operands
var stiOperand = OperandFactory.CreateFPURegisterOperand(stIndex);

3
X86DisassemblerTests/TestData/fnstsw_tests.csv
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@ -10,8 +10,7 @@ DFE0;[{ "Type": "Fnstsw", "Operands": ["ax"] }]
# FSTSW m2byte - Store FPU status word to memory
9BDD38;[{ "Type": "Fstsw", "Operands": ["word ptr [eax]"] }]
9BDD3C24;[{ "Type": "Fstsw", "Operands": ["word ptr [esp]"] }]
9BDD3C24;[{ "Type": "Fstsw", "Operands": ["word ptr [esp]"] }]
9BDD3C24;[{ "Type": "Fstsw", "Operands": ["word ptr [esp+0x00]"] }]
9BDD3B;[{ "Type": "Fstsw", "Operands": ["word ptr [ebx]"] }]
9BDD39;[{ "Type": "Fstsw", "Operands": ["word ptr [ecx]"] }]
9BDD3A;[{ "Type": "Fstsw", "Operands": ["word ptr [edx]"] }]

Can't render this file because it contains an unexpected character in line 6 and column 9.

4
X86DisassemblerTests/TestData/fstsw_tests.csv
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@ -10,8 +10,8 @@ DFE0;[{ "Type": "Fnstsw", "Operands": ["ax"] }]
# FSTSW m2byte - Store FPU status word to memory
9BDD38;[{ "Type": "Fstsw", "Operands": ["word ptr [eax]"] }]
9BDD3C24;[{ "Type": "Fstsw", "Operands": ["word ptr [esp]"] }]
9BDD7C24;[{ "Type": "Fstsw", "Operands": ["word ptr [esp]"] }]
9BDD3C24;[{ "Type": "Fstsw", "Operands": ["word ptr [esp+0x00]"] }]
9BDD7C24;[{ "Type": "Fstsw", "Operands": ["word ptr [esp+0x00]"] }]
9BDD3B;[{ "Type": "Fstsw", "Operands": ["word ptr [ebx]"] }]
9BDD39;[{ "Type": "Fstsw", "Operands": ["word ptr [ecx]"] }]
9BDD3A;[{ "Type": "Fstsw", "Operands": ["word ptr [edx]"] }]

Can't render this file because it contains an unexpected character in line 6 and column 9.