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float handlers

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bird_egop
2025-04-18 02:37:19 +03:00
parent 18ecf31c46
commit e967c0e0c0
27 changed files with 646 additions and 776 deletions
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40
X86Disassembler/X86/Handlers/FloatingPoint/Arithmetic/FaddFloat64Handler.cs
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@ -31,11 +31,13 @@ public class FaddFloat64Handler : InstructionHandler
return false;
}
// Check if the ModR/M byte has reg field = 0
// Check if the ModR/M byte has reg field = 0 and mod != 3 (memory operand)
byte modRm = Decoder.PeakByte();
byte reg = (byte)((modRm >> 3) & 0x7);
byte mod = (byte)((modRm >> 6) & 0x3);
return reg == 0;
// Only handle memory operands (mod != 3) with reg = 0
return reg == 0 && mod != 3;
}
/// <summary>
@ -54,37 +56,17 @@ public class FaddFloat64Handler : InstructionHandler
// Read the ModR/M byte using the specialized FPU method for 64-bit operands
var (mod, reg, fpuRm, rawOperand) = ModRMDecoder.ReadModRMFpu64();
// Verify reg field is 0 (FADD)
if (reg != 0)
{
return false;
}
// We've already verified reg field is 0 (FADD) in CanHandle
// and we only handle memory operands (mod != 3)
// Set the instruction type
instruction.Type = InstructionType.Fadd;
// For memory operands, set the operand
if (mod != 3) // Memory operand
{
// Set the structured operands - the operand already has the correct size from ReadModRM64
instruction.StructuredOperands =
[
rawOperand
];
}
else // Register operand (ST(i))
{
// For DC C0-DC FF, the operands are reversed: ST(i), ST(0)
var stiOperand = OperandFactory.CreateFPURegisterOperand(fpuRm); // ST(i)
var st0Operand = OperandFactory.CreateFPURegisterOperand(FpuRegisterIndex.ST0); // ST(0)
// Set the structured operands
instruction.StructuredOperands =
[
stiOperand,
st0Operand
];
}
// Set the structured operands - the operand already has the correct size from ReadModRMFpu64
instruction.StructuredOperands =
[
rawOperand
];
return true;
}