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f658f4384c
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cleanup
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2025-04-12 23:40:48 +03:00 |
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3cc6d27e33
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Split FloatingPointHandler into specialized handlers for each instruction type and fixed FLDCW instruction formatting
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2025-04-12 23:33:40 +03:00 |
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82653f96f2
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split float handlers
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2025-04-12 23:24:42 +03:00 |
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bb695cf3bb
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move handlers, remove bases
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2025-04-12 23:03:07 +03:00 |
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acccf5169a
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Fixed FnstswHandler test by registering the handler in InstructionHandlerFactory
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2025-04-12 22:34:02 +03:00 |
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c027adc113
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split and move handlers
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2025-04-12 22:18:46 +03:00 |
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0cc03c2479
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Added test for INT3 instruction handler
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2025-04-12 22:16:12 +03:00 |
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d5bcd56774
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Added tests for previously untested DataTransferHandler methods and fixed NOP instruction handling
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2025-04-12 22:05:51 +03:00 |
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a0e40c8a52
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Fixed instruction handlers and tests for Group1, Group3, and XOR instructions
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2025-04-12 21:48:41 +03:00 |
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794b56c6b5
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move handlers
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2025-04-12 21:34:16 +03:00 |
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a6b6cc1149
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Removed two-byte instruction handling from FloatingPointHandler. Simplified the code by removing the TwoByteInstructions dictionary and related methods since we now have dedicated handlers for specific instructions.
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2025-04-12 21:29:43 +03:00 |
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6ed6a7bd00
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Fixed floating point instruction handling. Removed redundant FNSTSW AX check from FloatingPointHandler and added dedicated test for FnstswHandler.
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2025-04-12 21:27:17 +03:00 |
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fe0b04f5a1
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Fixed TEST instruction handlers and tests. Updated TestImmWithRm8Handler and TestImmWithRm32Handler to properly check opcode in CanHandle and validate reg field in Decode. Improved test cases to use InstructionDecoder directly.
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2025-04-12 21:21:03 +03:00 |
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bf5fcdd2ff
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Fixed ConditionalJumpHandler to correctly implement x86 architecture specifications
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2025-04-12 21:09:41 +03:00 |
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bd251b6c06
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Improved ConditionalJumpHandler with better documentation and clearer code
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2025-04-12 21:02:52 +03:00 |
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0925bb7fef
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Fixed ConditionalJumpHandler to correctly display jump offset and added X86DisassemblerTests project to solution
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2025-04-12 21:00:32 +03:00 |
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87e0c152e2
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Fixed disassembler regression by adding handlers for TEST r/m8, r8 and TEST r/m8, imm8 instructions
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2025-04-12 20:32:38 +03:00 |
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dbc9b42007
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Removed obsolete handler classes and restored InstructionHandlerFactory
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2025-04-12 20:25:29 +03:00 |
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1442fd7060
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Removed obsolete Group1Handler and Group3Handler classes
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2025-04-12 20:14:28 +03:00 |
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e4b8645da0
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Implemented individual handlers for Group1 and Group3 instructions
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2025-04-12 20:13:01 +03:00 |
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58a148ebd8
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Refactor instruction handlers to use single instruction per handler pattern
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2025-04-12 19:57:42 +03:00 |
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82ffd51a3e
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Add support for RET instruction with immediate operand (0xC2)
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2025-04-12 19:36:46 +03:00 |
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0fb3fd7311
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Add support for XOR instruction
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2025-04-12 19:35:25 +03:00 |
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f3aa862a57
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Add support for two-byte conditional jumps, including JNZ (0F 85)
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2025-04-12 19:30:13 +03:00 |
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cedd7a931e
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Add support for TEST instruction
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2025-04-12 19:26:00 +03:00 |
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ae1c4730d0
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Add support for FNSTSW instruction
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2025-04-12 19:21:32 +03:00 |
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dffc405c10
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Refactored instruction decoder into smaller, more maintainable components using handler pattern
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2025-04-12 19:18:52 +03:00 |
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2e6e133159
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Added support for 0x83 opcode (Group 1 operations with sign-extended immediate)
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2025-04-12 19:04:43 +03:00 |
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1a76bb4e77
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Enhanced x86 instruction decoder to fully decode memory operands and match Ghidra output
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2025-04-12 18:55:54 +03:00 |
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3823121bea
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Added support for floating-point instructions including FISTP
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2025-04-12 18:52:55 +03:00 |
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9b5ec7e0d6
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Implemented enhanced x86 disassembler with improved instruction decoding and display
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2025-04-12 18:41:40 +03:00 |
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