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  • 8c15143933 Fix all tests #1 x86-disassembler bird_egop 2025-04-18 14:06:43 +03:00
  • d089fc9b28 fixes to FPU tests bird_egop 2025-04-18 13:47:34 +03:00
  • 8567cf1d6d Fix floating-point instruction memory operand test encodings bird_egop 2025-04-18 13:47:22 +03:00
  • 1536ce4385 Fix FSUB/FSUBR and FSUBP/FSUBRP instruction type handling bird_egop 2025-04-18 13:41:42 +03:00
  • 7bb14523e5 Fix FsubrStiStHandler to correctly use FSUB instruction type for DC E8-EF opcodes bird_egop 2025-04-18 13:31:23 +03:00
  • d25e7e8133 Fix FSTSW/FNSTSW memory operand encodings in test data bird_egop 2025-04-18 13:28:19 +03:00
  • 3cdd1fb2e6 Add handlers for FXTRACT and FPREM1 instructions bird_egop 2025-04-18 13:21:46 +03:00
  • adb37fe84f Standardize FPU instruction handler naming convention bird_egop 2025-04-18 13:19:28 +03:00
  • fea700596c Split FINIT/FNINIT handlers for proper instruction recognition bird_egop 2025-04-18 13:17:15 +03:00
  • 167b0e2c48 Fix floating-point instruction test encodings for memory operands bird_egop 2025-04-18 13:13:13 +03:00
  • 57d9a35ec5 Improve FCLEX/FNCLEX handler documentation with accurate behavior descriptions bird_egop 2025-04-18 13:09:39 +03:00
  • 6ea208d8bf Fix FCLEX/FNCLEX instruction types and rename handler for consistency bird_egop 2025-04-18 13:08:18 +03:00
  • a4de35cf41 Implement separate FSTSW handlers and fix test encodings bird_egop 2025-04-18 13:01:02 +03:00
  • cfef24f72d tests and handler fixes bird_egop 2025-04-18 12:49:10 +03:00
  • 4cb20cf741 Fix FNSTSW/FSTSW instruction encodings in test data bird_egop 2025-04-18 12:38:58 +03:00
  • e9c221ac14 Added flag manipulation instruction handlers (STC, CLC, CMC, STD, CLD, STI, CLI, SAHF, LAHF) bird_egop 2025-04-18 12:30:47 +03:00
  • e967c0e0c0 float handlers bird_egop 2025-04-18 02:37:19 +03:00
  • 18ecf31c46 Refactored floating point p-handlers with consistent naming convention bird_egop 2025-04-18 02:31:06 +03:00
  • 2a8cf9534e Fixed floating point comparison handlers for FCOM ST(i) and FCOMP ST(i) instructions bird_egop 2025-04-18 01:25:34 +03:00
  • 84d5652a62 remove duplicate registration bird_egop 2025-04-18 01:02:14 +03:00
  • 66f9e838ad Fixed floating point handlers for qword operands and added missing FCOM ST(0), ST(i) handler bird_egop 2025-04-18 00:44:57 +03:00
  • e6e3e886c8 Removed original floating point handlers that have been replaced by specialized handlers bird_egop 2025-04-18 00:23:21 +03:00
  • d216c29315 Refactored floating point instruction handlers for better organization and maintainability. Split generic handlers into specialized classes for DD and DF opcodes. bird_egop 2025-04-18 00:22:02 +03:00
  • ec56576116 Refactored floating point handlers into specialized classes for better organization and maintainability bird_egop 2025-04-17 23:57:16 +03:00
  • 5916d13995 Reorganize floating point handlers into logical subfolders bird_egop 2025-04-17 23:48:09 +03:00
  • 963248dca0 Refactor floating point handlers to use ReadModRMFpu method bird_egop 2025-04-17 23:33:56 +03:00
  • df453b930f fixes bird_egop 2025-04-17 22:54:19 +03:00
  • 4d2db05a07 Implemented additional SBB instruction handlers for register-register and register-memory operations bird_egop 2025-04-17 22:04:12 +03:00
  • 33dc0b0fa2 Implemented SBB instruction handlers for the x86 disassembler bird_egop 2025-04-17 21:49:44 +03:00
  • a62812f71c implement shift and rotate handlers. Fix tests bird_egop 2025-04-17 21:35:49 +03:00
  • a9d4c39717 add misc handlers, cleanup and fixes bird_egop 2025-04-17 20:47:51 +03:00
  • 124493cd94 Fixes to tests and ModRM + SIB bird_egop 2025-04-17 20:06:18 +03:00
  • 7c0e6d7f3a Added 16-bit register-to-register ADD handlers for r16, r/m16 and r/m16, r16 instructions bird_egop 2025-04-17 18:39:34 +03:00
  • dd97a00c2b Added 16-bit ADD handlers for r/m16, imm16 and r/m16, imm8 instructions bird_egop 2025-04-17 01:43:45 +03:00
  • 3fc0ebf1d5 Unified ADC accumulator handlers into a single handler bird_egop 2025-04-17 01:33:58 +03:00
  • 8c9b34ef09 Fixed PushImm16Handler registration order to correctly handle PUSH imm16 with operand size prefix bird_egop 2025-04-16 21:46:08 +03:00
  • fa1a7f582c Added support for far call instructions and PUSH imm16. Fixed invalid test cases in call_tests.csv and or_tests.csv bird_egop 2025-04-16 21:44:02 +03:00
  • 089fe4dfd4 Removed duplicate AndImmWithRm32Handler file bird_egop 2025-04-16 21:27:23 +03:00
  • b210764caa Removed duplicate AND handler and added detailed opcode comments to XOR handlers. Fixed potential naming inconsistencies in handler registrations. bird_egop 2025-04-16 21:25:46 +03:00
  • e8955b1ebd Improved code documentation in InstructionHandlerFactory. Added detailed opcode comments to handler registration lines and fixed duplicate handler registrations in RegisterAllHandlers method. bird_egop 2025-04-16 21:24:09 +03:00
  • 9096267f73 Added OrRm32R32Handler for OR r/m32, r32 (opcode 09) instruction and registered it in InstructionHandlerFactory. This fixes failing OR instruction tests. bird_egop 2025-04-16 21:20:40 +03:00
  • eac8e9ea69 Fixed NOT instruction tests with SIB byte encoding. Corrected memory addressing encodings for [eax] and displacement addressing. bird_egop 2025-04-16 21:17:48 +03:00
  • 226ec25549 Fixed DIV and IDIV instruction tests with SIB byte encoding. Corrected memory addressing encodings for [eax], [ebp], and displacement addressing. bird_egop 2025-04-16 21:16:31 +03:00
  • 9da33e12c4 Fixed IMUL instruction tests with SIB byte encoding. When using SIB byte with Base=101 (EBP) and Mod=00, it requires a 32-bit displacement. Replaced incorrect encodings with proper ones for [eax] addressing. bird_egop 2025-04-16 21:11:47 +03:00
  • 800915b534 new handlers and test fixes bird_egop 2025-04-16 20:54:08 +03:00
  • f654f64c71 Created dedicated Mul namespace for MUL instruction handlers. Implemented MulRm8Handler for MUL r/m8 instruction (opcode F6 /4) and moved MulRm32Handler to the new namespace. Updated InstructionHandlerFactory to register both handlers. bird_egop 2025-04-16 20:43:06 +03:00
  • be2dfc3dc5 Fixed MUL instruction tests with SIB byte encoding. When using SIB byte with Base=101 (EBP) and Mod=00, it requires a 32-bit displacement. Replaced incorrect encodings with proper ones for [eax] and direct memory addressing. bird_egop 2025-04-16 20:40:18 +03:00
  • 72ad1c0d90 Fixed NEG instruction tests with SIB byte encoding. When using SIB byte with Base=101 (EBP) and Mod=00, it requires a 32-bit displacement. Replaced incorrect encodings with proper ones for [eax] addressing. bird_egop 2025-04-16 20:37:46 +03:00
  • d2279f4720 Added NegRm8Handler for NEG r/m8 instruction (opcode F6 /3). Registered the new handler in InstructionHandlerFactory. bird_egop 2025-04-16 20:29:26 +03:00
  • f702e9da84 Fixed special case in MOV tests with EBP addressing. When Mod=00 and R/M=101 (EBP), it indicates a 32-bit displacement-only addressing mode, not [EBP]. Added correct test cases with Mod=01 and zero displacement. bird_egop 2025-04-16 20:27:00 +03:00
  • 41a4e5884d Fixed special case in INC/DEC tests with EBP addressing. When Mod=00 and R/M=101 (EBP), it indicates a 32-bit displacement-only addressing mode, not [EBP]. Added correct test cases with Mod=01 and zero displacement. bird_egop 2025-04-16 20:18:14 +03:00
  • 58b739d922 Fixed special case in LEA test with EBP addressing. When Mod=00 and R/M=101 (EBP), it indicates a 32-bit displacement-only addressing mode, not [EBP]. Added correct test case with Mod=01 and zero displacement. bird_egop 2025-04-16 20:16:31 +03:00
  • a474c4b7e4 Fixed invalid test cases in x86 disassembler tests. Added comments explaining special cases in x86 encoding and added valid test cases for LEA with different destination registers. bird_egop 2025-04-16 20:13:07 +03:00
  • 09786b781b Added detailed comments to test files explaining x86 encoding special cases: 1) Mod=00 and R/M=101 (EBP) for displacement-only addressing, 2) Mod=00 and R/M=100 (ESP) for SIB byte requirement, 3) SIB byte with EBP as base register special cases bird_egop 2025-04-16 19:58:34 +03:00
  • e5b63270b6 Added detailed comments explaining x86 ModR/M special cases: 1) Mod=00 and R/M=101 (EBP) for displacement-only addressing, 2) Mod=00 and R/M=100 (ESP) for SIB byte requirement bird_egop 2025-04-16 19:54:15 +03:00
  • 154e811d2d Added JmpRm32Handler for JMP r/m32 instructions (opcode FF /4) bird_egop 2025-04-16 19:50:00 +03:00
  • bc6d32a725 Fixed JP and JNP instruction types in TwoByteConditionalJumpHandler bird_egop 2025-04-16 19:44:37 +03:00
  • db96af74ff Fixed several instruction handling issues: 1) Added proper handling for zero displacements in memory operands, 2) Fixed large unsigned displacement values display, 3) Added CmpEaxImmHandler for CMP EAX, imm32 instruction, 4) Fixed JP and JNP conditional jump instruction types bird_egop 2025-04-16 19:43:03 +03:00
  • 193f9cd2d8 refactor modrm decoder more bird_egop 2025-04-16 19:14:11 +03:00
  • a91d6af8fc Refactored ModRMDecoder class into smaller, more focused components. Created RegisterMapper and SIBDecoder classes to improve maintainability. bird_egop 2025-04-16 19:11:36 +03:00
  • 9445fb225f fixes and removed unused code bird_egop 2025-04-16 19:07:32 +03:00
  • 9ddaa02471 Fixed ModRM handling for 8-bit operands with SIB byte. Updated test to match implementation. bird_egop 2025-04-16 18:42:15 +03:00
  • deb98183b1 more fixes bird_egop 2025-04-16 18:32:41 +03:00
  • 6719cff2af Test fixes bird_egop 2025-04-16 18:30:17 +03:00
  • d4eb920e2f Updated instruction handlers to use factory methods instead of directly setting Size property bird_egop 2025-04-16 01:39:23 +03:00
  • e06ea2beb3 Refactored register operands to separate 8-bit registers into dedicated Register8Operand class bird_egop 2025-04-16 01:10:33 +03:00
  • 46592d4877 fix various tests bird_egop 2025-04-15 23:54:51 +03:00
  • 4327464b98 add new add handlers bird_egop 2025-04-15 23:54:37 +03:00
  • 0dac4481f6 fix segment override tests according to ghidra bird_egop 2025-04-15 23:22:14 +03:00
  • 6882f0bd86 Update TestDataProvider to use CSV files directly from filesystem instead of embedded resources bird_egop 2025-04-15 23:21:52 +03:00
  • 61e92a50a5 Split FPU tests by instruction type for better organization and readability bird_egop 2025-04-15 22:45:09 +03:00
  • 0a2d551cb4 Enhanced test coverage for floating-point instructions bird_egop 2025-04-15 22:40:09 +03:00
  • 904f0eed47 Enhanced test coverage for DIV, flag control, and FNSTSW instructions bird_egop 2025-04-15 22:35:14 +03:00
  • 6169d68967 Enhanced test coverage for CMP, BIT and CALL instructions bird_egop 2025-04-15 22:32:37 +03:00
  • d6903f2e5b Enhanced test coverage for AND instructions bird_egop 2025-04-15 22:28:54 +03:00
  • 2fde1f2ae3 Enhanced test coverage for ADC and ADD instructions bird_egop 2025-04-15 22:27:51 +03:00
  • 2123ed2c5d add tons of tests bird_egop 2025-04-15 22:20:46 +03:00
  • abe4d38d4b more cleanup bird_egop 2025-04-15 02:42:47 +03:00
  • 49f1d7d221 cleanup bird_egop 2025-04-15 02:32:14 +03:00
  • 3ea327064a Fix x86 disassembler issues with direct memory addressing and immediate value formatting bird_egop 2025-04-15 02:29:32 +03:00
  • d351f41808 Fixed x86 disassembler issues: 1) Corrected ModRMDecoder to use RegisterIndex.Sp instead of RegisterIndex.Si for SIB detection 2) Updated floating point instruction handlers to use proper instruction types 3) Enhanced ImmediateOperand.ToString() to show full 32-bit representation for sign-extended values bird_egop 2025-04-15 00:14:28 +03:00
  • 9117830ff1 unbreak tests bird_egop 2025-04-14 23:08:52 +03:00
  • 685eeda03d Updated instruction handlers to use Type and StructuredOperands instead of Mnemonic and Operands bird_egop 2025-04-14 22:08:50 +03:00
  • c516e063e7 basic decompiler and fixes bird_egop 2025-04-14 02:07:17 +03:00
  • 157171fa90 remove more special cases. use standardized api bird_egop 2025-04-14 01:52:33 +03:00
  • c9e854a663 remove direct position changes from modrmdecoder bird_egop 2025-04-14 01:15:26 +03:00
  • 99b93523a4 more refactoring bird_egop 2025-04-14 01:08:14 +03:00
  • f54dc10596 Simplified XorImmWithRm16Handler by improving boundary checking and removing redundant code bird_egop 2025-04-14 01:01:31 +03:00
  • 4567465570 Simplified TestRegMemHandler by improving boundary checking and removing redundant code bird_egop 2025-04-14 00:56:57 +03:00
  • d3d2c4c63f Simplified TestRegMem8Handler by removing unused variables and improving code structure bird_egop 2025-04-14 00:54:16 +03:00
  • b7c6092b7f Simplified TEST instruction handlers by removing special cases and improving code structure bird_egop 2025-04-14 00:53:16 +03:00
  • dae52fc3ec Simplified SubImmFromRm32SignExtendedHandler by removing special case for operand type-based formatting bird_egop 2025-04-14 00:41:58 +03:00
  • 5b09d6f9b8 Simplified SubImmFromRm16SignExtendedHandler by removing special case for register name conversion bird_egop 2025-04-14 00:39:58 +03:00
  • 689195c6e5 Simplified SubImmFromRm16Handler by removing special case for register name conversion and improving boundary checking bird_egop 2025-04-14 00:38:47 +03:00
  • e134452eda Improved PUSH handlers by moving reg field check to CanHandle and adding proper boundary checking bird_egop 2025-04-14 00:33:39 +03:00
  • 53696a9f1c Removed special case check for 0x83 in OrRm8R8Handler to avoid introducing special cases in general solutions bird_egop 2025-04-14 00:30:53 +03:00
  • 243789892d Further simplified MultiByteNopHandler by using an array of tuples and matching patterns from longest to shortest bird_egop 2025-04-14 00:23:58 +03:00
  • 4b549f4b1b Simplified MultiByteNopHandler by using a dictionary-based approach to replace complex conditional logic bird_egop 2025-04-14 00:21:24 +03:00
  • c9901aa9b8 Simplified MovRm32Imm32Handler by improving boundary checking and error handling, and updated test to match expected behavior bird_egop 2025-04-14 00:19:36 +03:00
  • 2d0f701dd1 Simplified TwoByteConditionalJumpHandler and MovRegMemHandler by improving boundary checking and target address calculation bird_egop 2025-04-14 00:17:31 +03:00