bird_egop
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adb37fe84f
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Standardize FPU instruction handler naming convention
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2025-04-18 13:19:28 +03:00 |
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bird_egop
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fea700596c
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Split FINIT/FNINIT handlers for proper instruction recognition
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2025-04-18 13:17:15 +03:00 |
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bird_egop
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167b0e2c48
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Fix floating-point instruction test encodings for memory operands
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2025-04-18 13:13:13 +03:00 |
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bird_egop
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57d9a35ec5
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Improve FCLEX/FNCLEX handler documentation with accurate behavior descriptions
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2025-04-18 13:09:39 +03:00 |
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bird_egop
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6ea208d8bf
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Fix FCLEX/FNCLEX instruction types and rename handler for consistency
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2025-04-18 13:08:18 +03:00 |
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bird_egop
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a4de35cf41
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Implement separate FSTSW handlers and fix test encodings
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2025-04-18 13:01:02 +03:00 |
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bird_egop
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cfef24f72d
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tests and handler fixes
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2025-04-18 12:49:43 +03:00 |
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bird_egop
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4cb20cf741
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Fix FNSTSW/FSTSW instruction encodings in test data
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2025-04-18 12:38:58 +03:00 |
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bird_egop
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e9c221ac14
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Added flag manipulation instruction handlers (STC, CLC, CMC, STD, CLD, STI, CLI, SAHF, LAHF)
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2025-04-18 12:30:47 +03:00 |
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bird_egop
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e967c0e0c0
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float handlers
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2025-04-18 02:37:19 +03:00 |
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bird_egop
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18ecf31c46
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Refactored floating point p-handlers with consistent naming convention
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2025-04-18 02:31:06 +03:00 |
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bird_egop
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2a8cf9534e
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Fixed floating point comparison handlers for FCOM ST(i) and FCOMP ST(i) instructions
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2025-04-18 01:25:34 +03:00 |
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bird_egop
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84d5652a62
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remove duplicate registration
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2025-04-18 01:02:14 +03:00 |
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bird_egop
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66f9e838ad
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Fixed floating point handlers for qword operands and added missing FCOM ST(0), ST(i) handler
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2025-04-18 00:44:57 +03:00 |
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bird_egop
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e6e3e886c8
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Removed original floating point handlers that have been replaced by specialized handlers
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2025-04-18 00:23:21 +03:00 |
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bird_egop
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d216c29315
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Refactored floating point instruction handlers for better organization and maintainability. Split generic handlers into specialized classes for DD and DF opcodes.
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2025-04-18 00:22:02 +03:00 |
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bird_egop
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ec56576116
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Refactored floating point handlers into specialized classes for better organization and maintainability
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2025-04-17 23:57:16 +03:00 |
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bird_egop
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5916d13995
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Reorganize floating point handlers into logical subfolders
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2025-04-17 23:48:09 +03:00 |
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bird_egop
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963248dca0
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Refactor floating point handlers to use ReadModRMFpu method
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2025-04-17 23:33:56 +03:00 |
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bird_egop
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df453b930f
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fixes
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2025-04-17 22:56:05 +03:00 |
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bird_egop
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4d2db05a07
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Implemented additional SBB instruction handlers for register-register and register-memory operations
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2025-04-17 22:04:12 +03:00 |
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bird_egop
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33dc0b0fa2
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Implemented SBB instruction handlers for the x86 disassembler
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2025-04-17 21:49:44 +03:00 |
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bird_egop
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a62812f71c
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implement shift and rotate handlers. Fix tests
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2025-04-17 21:35:49 +03:00 |
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bird_egop
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a9d4c39717
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add misc handlers, cleanup and fixes
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2025-04-17 20:47:51 +03:00 |
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bird_egop
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124493cd94
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Fixes to tests and ModRM + SIB
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2025-04-17 20:06:18 +03:00 |
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bird_egop
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7c0e6d7f3a
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Added 16-bit register-to-register ADD handlers for r16, r/m16 and r/m16, r16 instructions
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2025-04-17 18:39:34 +03:00 |
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bird_egop
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dd97a00c2b
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Added 16-bit ADD handlers for r/m16, imm16 and r/m16, imm8 instructions
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2025-04-17 01:43:45 +03:00 |
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bird_egop
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3fc0ebf1d5
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Unified ADC accumulator handlers into a single handler
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2025-04-17 01:34:08 +03:00 |
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bird_egop
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8c9b34ef09
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Fixed PushImm16Handler registration order to correctly handle PUSH imm16 with operand size prefix
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2025-04-16 21:46:08 +03:00 |
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bird_egop
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fa1a7f582c
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Added support for far call instructions and PUSH imm16. Fixed invalid test cases in call_tests.csv and or_tests.csv
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2025-04-16 21:44:02 +03:00 |
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bird_egop
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089fe4dfd4
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Removed duplicate AndImmWithRm32Handler file
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2025-04-16 21:27:23 +03:00 |
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bird_egop
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b210764caa
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Removed duplicate AND handler and added detailed opcode comments to XOR handlers. Fixed potential naming inconsistencies in handler registrations.
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2025-04-16 21:25:46 +03:00 |
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bird_egop
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e8955b1ebd
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Improved code documentation in InstructionHandlerFactory. Added detailed opcode comments to handler registration lines and fixed duplicate handler registrations in RegisterAllHandlers method.
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2025-04-16 21:24:09 +03:00 |
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bird_egop
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9096267f73
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Added OrRm32R32Handler for OR r/m32, r32 (opcode 09) instruction and registered it in InstructionHandlerFactory. This fixes failing OR instruction tests.
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2025-04-16 21:20:40 +03:00 |
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bird_egop
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eac8e9ea69
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Fixed NOT instruction tests with SIB byte encoding. Corrected memory addressing encodings for [eax] and displacement addressing.
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2025-04-16 21:17:48 +03:00 |
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bird_egop
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226ec25549
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Fixed DIV and IDIV instruction tests with SIB byte encoding. Corrected memory addressing encodings for [eax], [ebp], and displacement addressing.
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2025-04-16 21:16:31 +03:00 |
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bird_egop
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9da33e12c4
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Fixed IMUL instruction tests with SIB byte encoding. When using SIB byte with Base=101 (EBP) and Mod=00, it requires a 32-bit displacement. Replaced incorrect encodings with proper ones for [eax] addressing.
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2025-04-16 21:11:47 +03:00 |
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bird_egop
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800915b534
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new handlers and test fixes
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2025-04-16 20:54:08 +03:00 |
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bird_egop
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f654f64c71
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Created dedicated Mul namespace for MUL instruction handlers. Implemented MulRm8Handler for MUL r/m8 instruction (opcode F6 /4) and moved MulRm32Handler to the new namespace. Updated InstructionHandlerFactory to register both handlers.
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2025-04-16 20:43:06 +03:00 |
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bird_egop
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be2dfc3dc5
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Fixed MUL instruction tests with SIB byte encoding. When using SIB byte with Base=101 (EBP) and Mod=00, it requires a 32-bit displacement. Replaced incorrect encodings with proper ones for [eax] and direct memory addressing.
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2025-04-16 20:40:18 +03:00 |
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bird_egop
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72ad1c0d90
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Fixed NEG instruction tests with SIB byte encoding. When using SIB byte with Base=101 (EBP) and Mod=00, it requires a 32-bit displacement. Replaced incorrect encodings with proper ones for [eax] addressing.
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2025-04-16 20:37:46 +03:00 |
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bird_egop
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d2279f4720
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Added NegRm8Handler for NEG r/m8 instruction (opcode F6 /3). Registered the new handler in InstructionHandlerFactory.
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2025-04-16 20:29:26 +03:00 |
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bird_egop
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f702e9da84
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Fixed special case in MOV tests with EBP addressing. When Mod=00 and R/M=101 (EBP), it indicates a 32-bit displacement-only addressing mode, not [EBP]. Added correct test cases with Mod=01 and zero displacement.
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2025-04-16 20:27:00 +03:00 |
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bird_egop
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41a4e5884d
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Fixed special case in INC/DEC tests with EBP addressing. When Mod=00 and R/M=101 (EBP), it indicates a 32-bit displacement-only addressing mode, not [EBP]. Added correct test cases with Mod=01 and zero displacement.
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2025-04-16 20:18:14 +03:00 |
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bird_egop
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58b739d922
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Fixed special case in LEA test with EBP addressing. When Mod=00 and R/M=101 (EBP), it indicates a 32-bit displacement-only addressing mode, not [EBP]. Added correct test case with Mod=01 and zero displacement.
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2025-04-16 20:16:31 +03:00 |
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bird_egop
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a474c4b7e4
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Fixed invalid test cases in x86 disassembler tests. Added comments explaining special cases in x86 encoding and added valid test cases for LEA with different destination registers.
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2025-04-16 20:13:07 +03:00 |
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bird_egop
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09786b781b
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Added detailed comments to test files explaining x86 encoding special cases: 1) Mod=00 and R/M=101 (EBP) for displacement-only addressing, 2) Mod=00 and R/M=100 (ESP) for SIB byte requirement, 3) SIB byte with EBP as base register special cases
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2025-04-16 19:58:34 +03:00 |
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bird_egop
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e5b63270b6
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Added detailed comments explaining x86 ModR/M special cases: 1) Mod=00 and R/M=101 (EBP) for displacement-only addressing, 2) Mod=00 and R/M=100 (ESP) for SIB byte requirement
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2025-04-16 19:54:15 +03:00 |
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bird_egop
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154e811d2d
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Added JmpRm32Handler for JMP r/m32 instructions (opcode FF /4)
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2025-04-16 19:50:00 +03:00 |
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bird_egop
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bc6d32a725
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Fixed JP and JNP instruction types in TwoByteConditionalJumpHandler
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2025-04-16 19:44:37 +03:00 |
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