bird_egop
|
fea700596c
|
Split FINIT/FNINIT handlers for proper instruction recognition
|
2025-04-18 13:17:15 +03:00 |
|
bird_egop
|
167b0e2c48
|
Fix floating-point instruction test encodings for memory operands
|
2025-04-18 13:13:13 +03:00 |
|
bird_egop
|
57d9a35ec5
|
Improve FCLEX/FNCLEX handler documentation with accurate behavior descriptions
|
2025-04-18 13:09:39 +03:00 |
|
bird_egop
|
6ea208d8bf
|
Fix FCLEX/FNCLEX instruction types and rename handler for consistency
|
2025-04-18 13:08:18 +03:00 |
|
bird_egop
|
a4de35cf41
|
Implement separate FSTSW handlers and fix test encodings
|
2025-04-18 13:01:02 +03:00 |
|
bird_egop
|
cfef24f72d
|
tests and handler fixes
|
2025-04-18 12:49:43 +03:00 |
|
bird_egop
|
4cb20cf741
|
Fix FNSTSW/FSTSW instruction encodings in test data
|
2025-04-18 12:38:58 +03:00 |
|
bird_egop
|
e9c221ac14
|
Added flag manipulation instruction handlers (STC, CLC, CMC, STD, CLD, STI, CLI, SAHF, LAHF)
|
2025-04-18 12:30:47 +03:00 |
|
bird_egop
|
e967c0e0c0
|
float handlers
|
2025-04-18 02:37:19 +03:00 |
|
bird_egop
|
18ecf31c46
|
Refactored floating point p-handlers with consistent naming convention
|
2025-04-18 02:31:06 +03:00 |
|
bird_egop
|
2a8cf9534e
|
Fixed floating point comparison handlers for FCOM ST(i) and FCOMP ST(i) instructions
|
2025-04-18 01:25:34 +03:00 |
|
bird_egop
|
84d5652a62
|
remove duplicate registration
|
2025-04-18 01:02:14 +03:00 |
|
bird_egop
|
66f9e838ad
|
Fixed floating point handlers for qword operands and added missing FCOM ST(0), ST(i) handler
|
2025-04-18 00:44:57 +03:00 |
|
bird_egop
|
e6e3e886c8
|
Removed original floating point handlers that have been replaced by specialized handlers
|
2025-04-18 00:23:21 +03:00 |
|
bird_egop
|
d216c29315
|
Refactored floating point instruction handlers for better organization and maintainability. Split generic handlers into specialized classes for DD and DF opcodes.
|
2025-04-18 00:22:02 +03:00 |
|
bird_egop
|
ec56576116
|
Refactored floating point handlers into specialized classes for better organization and maintainability
|
2025-04-17 23:57:16 +03:00 |
|
bird_egop
|
5916d13995
|
Reorganize floating point handlers into logical subfolders
|
2025-04-17 23:48:09 +03:00 |
|
bird_egop
|
963248dca0
|
Refactor floating point handlers to use ReadModRMFpu method
|
2025-04-17 23:33:56 +03:00 |
|
bird_egop
|
df453b930f
|
fixes
|
2025-04-17 22:56:05 +03:00 |
|
bird_egop
|
4d2db05a07
|
Implemented additional SBB instruction handlers for register-register and register-memory operations
|
2025-04-17 22:04:12 +03:00 |
|
bird_egop
|
33dc0b0fa2
|
Implemented SBB instruction handlers for the x86 disassembler
|
2025-04-17 21:49:44 +03:00 |
|
bird_egop
|
a62812f71c
|
implement shift and rotate handlers. Fix tests
|
2025-04-17 21:35:49 +03:00 |
|
bird_egop
|
a9d4c39717
|
add misc handlers, cleanup and fixes
|
2025-04-17 20:47:51 +03:00 |
|
bird_egop
|
124493cd94
|
Fixes to tests and ModRM + SIB
|
2025-04-17 20:06:18 +03:00 |
|
bird_egop
|
7c0e6d7f3a
|
Added 16-bit register-to-register ADD handlers for r16, r/m16 and r/m16, r16 instructions
|
2025-04-17 18:39:34 +03:00 |
|
bird_egop
|
dd97a00c2b
|
Added 16-bit ADD handlers for r/m16, imm16 and r/m16, imm8 instructions
|
2025-04-17 01:43:45 +03:00 |
|
bird_egop
|
3fc0ebf1d5
|
Unified ADC accumulator handlers into a single handler
|
2025-04-17 01:34:08 +03:00 |
|
bird_egop
|
8c9b34ef09
|
Fixed PushImm16Handler registration order to correctly handle PUSH imm16 with operand size prefix
|
2025-04-16 21:46:08 +03:00 |
|
bird_egop
|
fa1a7f582c
|
Added support for far call instructions and PUSH imm16. Fixed invalid test cases in call_tests.csv and or_tests.csv
|
2025-04-16 21:44:02 +03:00 |
|
bird_egop
|
089fe4dfd4
|
Removed duplicate AndImmWithRm32Handler file
|
2025-04-16 21:27:23 +03:00 |
|
bird_egop
|
b210764caa
|
Removed duplicate AND handler and added detailed opcode comments to XOR handlers. Fixed potential naming inconsistencies in handler registrations.
|
2025-04-16 21:25:46 +03:00 |
|
bird_egop
|
e8955b1ebd
|
Improved code documentation in InstructionHandlerFactory. Added detailed opcode comments to handler registration lines and fixed duplicate handler registrations in RegisterAllHandlers method.
|
2025-04-16 21:24:09 +03:00 |
|
bird_egop
|
9096267f73
|
Added OrRm32R32Handler for OR r/m32, r32 (opcode 09) instruction and registered it in InstructionHandlerFactory. This fixes failing OR instruction tests.
|
2025-04-16 21:20:40 +03:00 |
|
bird_egop
|
eac8e9ea69
|
Fixed NOT instruction tests with SIB byte encoding. Corrected memory addressing encodings for [eax] and displacement addressing.
|
2025-04-16 21:17:48 +03:00 |
|
bird_egop
|
226ec25549
|
Fixed DIV and IDIV instruction tests with SIB byte encoding. Corrected memory addressing encodings for [eax], [ebp], and displacement addressing.
|
2025-04-16 21:16:31 +03:00 |
|
bird_egop
|
9da33e12c4
|
Fixed IMUL instruction tests with SIB byte encoding. When using SIB byte with Base=101 (EBP) and Mod=00, it requires a 32-bit displacement. Replaced incorrect encodings with proper ones for [eax] addressing.
|
2025-04-16 21:11:47 +03:00 |
|
bird_egop
|
800915b534
|
new handlers and test fixes
|
2025-04-16 20:54:08 +03:00 |
|
bird_egop
|
f654f64c71
|
Created dedicated Mul namespace for MUL instruction handlers. Implemented MulRm8Handler for MUL r/m8 instruction (opcode F6 /4) and moved MulRm32Handler to the new namespace. Updated InstructionHandlerFactory to register both handlers.
|
2025-04-16 20:43:06 +03:00 |
|
bird_egop
|
be2dfc3dc5
|
Fixed MUL instruction tests with SIB byte encoding. When using SIB byte with Base=101 (EBP) and Mod=00, it requires a 32-bit displacement. Replaced incorrect encodings with proper ones for [eax] and direct memory addressing.
|
2025-04-16 20:40:18 +03:00 |
|
bird_egop
|
72ad1c0d90
|
Fixed NEG instruction tests with SIB byte encoding. When using SIB byte with Base=101 (EBP) and Mod=00, it requires a 32-bit displacement. Replaced incorrect encodings with proper ones for [eax] addressing.
|
2025-04-16 20:37:46 +03:00 |
|
bird_egop
|
d2279f4720
|
Added NegRm8Handler for NEG r/m8 instruction (opcode F6 /3). Registered the new handler in InstructionHandlerFactory.
|
2025-04-16 20:29:26 +03:00 |
|
bird_egop
|
f702e9da84
|
Fixed special case in MOV tests with EBP addressing. When Mod=00 and R/M=101 (EBP), it indicates a 32-bit displacement-only addressing mode, not [EBP]. Added correct test cases with Mod=01 and zero displacement.
|
2025-04-16 20:27:00 +03:00 |
|
bird_egop
|
41a4e5884d
|
Fixed special case in INC/DEC tests with EBP addressing. When Mod=00 and R/M=101 (EBP), it indicates a 32-bit displacement-only addressing mode, not [EBP]. Added correct test cases with Mod=01 and zero displacement.
|
2025-04-16 20:18:14 +03:00 |
|
bird_egop
|
58b739d922
|
Fixed special case in LEA test with EBP addressing. When Mod=00 and R/M=101 (EBP), it indicates a 32-bit displacement-only addressing mode, not [EBP]. Added correct test case with Mod=01 and zero displacement.
|
2025-04-16 20:16:31 +03:00 |
|
bird_egop
|
a474c4b7e4
|
Fixed invalid test cases in x86 disassembler tests. Added comments explaining special cases in x86 encoding and added valid test cases for LEA with different destination registers.
|
2025-04-16 20:13:07 +03:00 |
|
bird_egop
|
09786b781b
|
Added detailed comments to test files explaining x86 encoding special cases: 1) Mod=00 and R/M=101 (EBP) for displacement-only addressing, 2) Mod=00 and R/M=100 (ESP) for SIB byte requirement, 3) SIB byte with EBP as base register special cases
|
2025-04-16 19:58:34 +03:00 |
|
bird_egop
|
e5b63270b6
|
Added detailed comments explaining x86 ModR/M special cases: 1) Mod=00 and R/M=101 (EBP) for displacement-only addressing, 2) Mod=00 and R/M=100 (ESP) for SIB byte requirement
|
2025-04-16 19:54:15 +03:00 |
|
bird_egop
|
154e811d2d
|
Added JmpRm32Handler for JMP r/m32 instructions (opcode FF /4)
|
2025-04-16 19:50:00 +03:00 |
|
bird_egop
|
bc6d32a725
|
Fixed JP and JNP instruction types in TwoByteConditionalJumpHandler
|
2025-04-16 19:44:37 +03:00 |
|
bird_egop
|
db96af74ff
|
Fixed several instruction handling issues: 1) Added proper handling for zero displacements in memory operands, 2) Fixed large unsigned displacement values display, 3) Added CmpEaxImmHandler for CMP EAX, imm32 instruction, 4) Fixed JP and JNP conditional jump instruction types
|
2025-04-16 19:43:03 +03:00 |
|