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mirror of https://github.com/sampletext32/ParkanPlayground.git synced 2025-06-19 16:08:02 +03:00
Commit Graph

184 Commits

Author SHA1 Message Date
57d9a35ec5 Improve FCLEX/FNCLEX handler documentation with accurate behavior descriptions 2025-04-18 13:09:39 +03:00
6ea208d8bf Fix FCLEX/FNCLEX instruction types and rename handler for consistency 2025-04-18 13:08:18 +03:00
a4de35cf41 Implement separate FSTSW handlers and fix test encodings 2025-04-18 13:01:02 +03:00
cfef24f72d tests and handler fixes 2025-04-18 12:49:43 +03:00
e9c221ac14 Added flag manipulation instruction handlers (STC, CLC, CMC, STD, CLD, STI, CLI, SAHF, LAHF) 2025-04-18 12:30:47 +03:00
e967c0e0c0 float handlers 2025-04-18 02:37:19 +03:00
18ecf31c46 Refactored floating point p-handlers with consistent naming convention 2025-04-18 02:31:06 +03:00
2a8cf9534e Fixed floating point comparison handlers for FCOM ST(i) and FCOMP ST(i) instructions 2025-04-18 01:25:34 +03:00
84d5652a62 remove duplicate registration 2025-04-18 01:02:14 +03:00
66f9e838ad Fixed floating point handlers for qword operands and added missing FCOM ST(0), ST(i) handler 2025-04-18 00:44:57 +03:00
e6e3e886c8 Removed original floating point handlers that have been replaced by specialized handlers 2025-04-18 00:23:21 +03:00
d216c29315 Refactored floating point instruction handlers for better organization and maintainability. Split generic handlers into specialized classes for DD and DF opcodes. 2025-04-18 00:22:02 +03:00
ec56576116 Refactored floating point handlers into specialized classes for better organization and maintainability 2025-04-17 23:57:16 +03:00
5916d13995 Reorganize floating point handlers into logical subfolders 2025-04-17 23:48:09 +03:00
963248dca0 Refactor floating point handlers to use ReadModRMFpu method 2025-04-17 23:33:56 +03:00
df453b930f fixes 2025-04-17 22:56:05 +03:00
4d2db05a07 Implemented additional SBB instruction handlers for register-register and register-memory operations 2025-04-17 22:04:12 +03:00
33dc0b0fa2 Implemented SBB instruction handlers for the x86 disassembler 2025-04-17 21:49:44 +03:00
a62812f71c implement shift and rotate handlers. Fix tests 2025-04-17 21:35:49 +03:00
a9d4c39717 add misc handlers, cleanup and fixes 2025-04-17 20:47:51 +03:00
124493cd94 Fixes to tests and ModRM + SIB 2025-04-17 20:06:18 +03:00
7c0e6d7f3a Added 16-bit register-to-register ADD handlers for r16, r/m16 and r/m16, r16 instructions 2025-04-17 18:39:34 +03:00
dd97a00c2b Added 16-bit ADD handlers for r/m16, imm16 and r/m16, imm8 instructions 2025-04-17 01:43:45 +03:00
3fc0ebf1d5 Unified ADC accumulator handlers into a single handler 2025-04-17 01:34:08 +03:00
8c9b34ef09 Fixed PushImm16Handler registration order to correctly handle PUSH imm16 with operand size prefix 2025-04-16 21:46:08 +03:00
fa1a7f582c Added support for far call instructions and PUSH imm16. Fixed invalid test cases in call_tests.csv and or_tests.csv 2025-04-16 21:44:02 +03:00
089fe4dfd4 Removed duplicate AndImmWithRm32Handler file 2025-04-16 21:27:23 +03:00
b210764caa Removed duplicate AND handler and added detailed opcode comments to XOR handlers. Fixed potential naming inconsistencies in handler registrations. 2025-04-16 21:25:46 +03:00
e8955b1ebd Improved code documentation in InstructionHandlerFactory. Added detailed opcode comments to handler registration lines and fixed duplicate handler registrations in RegisterAllHandlers method. 2025-04-16 21:24:09 +03:00
9096267f73 Added OrRm32R32Handler for OR r/m32, r32 (opcode 09) instruction and registered it in InstructionHandlerFactory. This fixes failing OR instruction tests. 2025-04-16 21:20:40 +03:00
800915b534 new handlers and test fixes 2025-04-16 20:54:08 +03:00
f654f64c71 Created dedicated Mul namespace for MUL instruction handlers. Implemented MulRm8Handler for MUL r/m8 instruction (opcode F6 /4) and moved MulRm32Handler to the new namespace. Updated InstructionHandlerFactory to register both handlers. 2025-04-16 20:43:06 +03:00
d2279f4720 Added NegRm8Handler for NEG r/m8 instruction (opcode F6 /3). Registered the new handler in InstructionHandlerFactory. 2025-04-16 20:29:26 +03:00
e5b63270b6 Added detailed comments explaining x86 ModR/M special cases: 1) Mod=00 and R/M=101 (EBP) for displacement-only addressing, 2) Mod=00 and R/M=100 (ESP) for SIB byte requirement 2025-04-16 19:54:15 +03:00
154e811d2d Added JmpRm32Handler for JMP r/m32 instructions (opcode FF /4) 2025-04-16 19:50:00 +03:00
bc6d32a725 Fixed JP and JNP instruction types in TwoByteConditionalJumpHandler 2025-04-16 19:44:37 +03:00
db96af74ff Fixed several instruction handling issues: 1) Added proper handling for zero displacements in memory operands, 2) Fixed large unsigned displacement values display, 3) Added CmpEaxImmHandler for CMP EAX, imm32 instruction, 4) Fixed JP and JNP conditional jump instruction types 2025-04-16 19:43:03 +03:00
193f9cd2d8 refactor modrm decoder more 2025-04-16 19:14:11 +03:00
a91d6af8fc Refactored ModRMDecoder class into smaller, more focused components. Created RegisterMapper and SIBDecoder classes to improve maintainability. 2025-04-16 19:11:36 +03:00
9445fb225f fixes and removed unused code 2025-04-16 19:07:32 +03:00
9ddaa02471 Fixed ModRM handling for 8-bit operands with SIB byte. Updated test to match implementation. 2025-04-16 18:42:15 +03:00
6719cff2af Test fixes 2025-04-16 18:30:17 +03:00
d4eb920e2f Updated instruction handlers to use factory methods instead of directly setting Size property 2025-04-16 01:39:23 +03:00
e06ea2beb3 Refactored register operands to separate 8-bit registers into dedicated Register8Operand class 2025-04-16 01:10:33 +03:00
46592d4877 fix various tests 2025-04-15 23:54:51 +03:00
4327464b98 add new add handlers 2025-04-15 23:54:37 +03:00
6882f0bd86 Update TestDataProvider to use CSV files directly from filesystem instead of embedded resources 2025-04-15 23:21:52 +03:00
2123ed2c5d add tons of tests 2025-04-15 22:20:46 +03:00
abe4d38d4b more cleanup 2025-04-15 02:42:47 +03:00
49f1d7d221 cleanup 2025-04-15 02:32:14 +03:00