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e137deff7e
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implement NRES packing
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2025-06-22 18:47:21 +03:00 |
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c044db1b96
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refactorings
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2025-04-20 19:54:52 +03:00 |
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1c7054781c
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changes all over the place
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2025-04-19 02:12:46 +03:00 |
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de2e4312fb
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decompiler iter1
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2025-04-18 23:46:51 +03:00 |
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0ddbfd2951
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Enhance control flow analysis and pseudocode generation
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2025-04-18 21:52:48 +03:00 |
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883f3a2659
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Improve decompiler output and reduce verbosity
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2025-04-18 21:42:25 +03:00 |
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c7fd962d90
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Fix address conversion in BlockDisassembler to properly handle RVA addresses and ensure entry blocks are correctly identified
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2025-04-18 21:34:35 +03:00 |
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7eead316cd
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t
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2025-04-18 16:29:53 +03:00 |
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23fb497e0a
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Remove debug output from Disassembler for cleaner output
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2025-04-18 14:20:15 +03:00 |
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54a0a3e9c0
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Fix RVA to offset calculation for control flow-based disassembly
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2025-04-18 14:19:13 +03:00 |
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8c15143933
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Fix all tests
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2025-04-18 14:06:43 +03:00 |
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d089fc9b28
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fixes to FPU tests
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2025-04-18 13:47:34 +03:00 |
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1536ce4385
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Fix FSUB/FSUBR and FSUBP/FSUBRP instruction type handling
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2025-04-18 13:41:42 +03:00 |
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7bb14523e5
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Fix FsubrStiStHandler to correctly use FSUB instruction type for DC E8-EF opcodes
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2025-04-18 13:31:23 +03:00 |
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3cdd1fb2e6
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Add handlers for FXTRACT and FPREM1 instructions
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2025-04-18 13:21:46 +03:00 |
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adb37fe84f
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Standardize FPU instruction handler naming convention
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2025-04-18 13:19:28 +03:00 |
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fea700596c
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Split FINIT/FNINIT handlers for proper instruction recognition
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2025-04-18 13:17:15 +03:00 |
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57d9a35ec5
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Improve FCLEX/FNCLEX handler documentation with accurate behavior descriptions
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2025-04-18 13:09:39 +03:00 |
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6ea208d8bf
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Fix FCLEX/FNCLEX instruction types and rename handler for consistency
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2025-04-18 13:08:18 +03:00 |
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a4de35cf41
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Implement separate FSTSW handlers and fix test encodings
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2025-04-18 13:01:02 +03:00 |
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cfef24f72d
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tests and handler fixes
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2025-04-18 12:49:43 +03:00 |
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e9c221ac14
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Added flag manipulation instruction handlers (STC, CLC, CMC, STD, CLD, STI, CLI, SAHF, LAHF)
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2025-04-18 12:30:47 +03:00 |
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e967c0e0c0
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float handlers
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2025-04-18 02:37:19 +03:00 |
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18ecf31c46
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Refactored floating point p-handlers with consistent naming convention
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2025-04-18 02:31:06 +03:00 |
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2a8cf9534e
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Fixed floating point comparison handlers for FCOM ST(i) and FCOMP ST(i) instructions
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2025-04-18 01:25:34 +03:00 |
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84d5652a62
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remove duplicate registration
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2025-04-18 01:02:14 +03:00 |
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66f9e838ad
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Fixed floating point handlers for qword operands and added missing FCOM ST(0), ST(i) handler
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2025-04-18 00:44:57 +03:00 |
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e6e3e886c8
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Removed original floating point handlers that have been replaced by specialized handlers
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2025-04-18 00:23:21 +03:00 |
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d216c29315
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Refactored floating point instruction handlers for better organization and maintainability. Split generic handlers into specialized classes for DD and DF opcodes.
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2025-04-18 00:22:02 +03:00 |
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ec56576116
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Refactored floating point handlers into specialized classes for better organization and maintainability
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2025-04-17 23:57:16 +03:00 |
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5916d13995
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Reorganize floating point handlers into logical subfolders
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2025-04-17 23:48:09 +03:00 |
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963248dca0
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Refactor floating point handlers to use ReadModRMFpu method
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2025-04-17 23:33:56 +03:00 |
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df453b930f
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fixes
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2025-04-17 22:56:05 +03:00 |
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4d2db05a07
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Implemented additional SBB instruction handlers for register-register and register-memory operations
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2025-04-17 22:04:12 +03:00 |
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33dc0b0fa2
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Implemented SBB instruction handlers for the x86 disassembler
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2025-04-17 21:49:44 +03:00 |
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a62812f71c
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implement shift and rotate handlers. Fix tests
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2025-04-17 21:35:49 +03:00 |
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a9d4c39717
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add misc handlers, cleanup and fixes
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2025-04-17 20:47:51 +03:00 |
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124493cd94
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Fixes to tests and ModRM + SIB
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2025-04-17 20:06:18 +03:00 |
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7c0e6d7f3a
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Added 16-bit register-to-register ADD handlers for r16, r/m16 and r/m16, r16 instructions
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2025-04-17 18:39:34 +03:00 |
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dd97a00c2b
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Added 16-bit ADD handlers for r/m16, imm16 and r/m16, imm8 instructions
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2025-04-17 01:43:45 +03:00 |
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3fc0ebf1d5
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Unified ADC accumulator handlers into a single handler
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2025-04-17 01:34:08 +03:00 |
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8c9b34ef09
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Fixed PushImm16Handler registration order to correctly handle PUSH imm16 with operand size prefix
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2025-04-16 21:46:08 +03:00 |
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fa1a7f582c
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Added support for far call instructions and PUSH imm16. Fixed invalid test cases in call_tests.csv and or_tests.csv
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2025-04-16 21:44:02 +03:00 |
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089fe4dfd4
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Removed duplicate AndImmWithRm32Handler file
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2025-04-16 21:27:23 +03:00 |
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b210764caa
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Removed duplicate AND handler and added detailed opcode comments to XOR handlers. Fixed potential naming inconsistencies in handler registrations.
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2025-04-16 21:25:46 +03:00 |
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e8955b1ebd
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Improved code documentation in InstructionHandlerFactory. Added detailed opcode comments to handler registration lines and fixed duplicate handler registrations in RegisterAllHandlers method.
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2025-04-16 21:24:09 +03:00 |
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9096267f73
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Added OrRm32R32Handler for OR r/m32, r32 (opcode 09) instruction and registered it in InstructionHandlerFactory. This fixes failing OR instruction tests.
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2025-04-16 21:20:40 +03:00 |
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800915b534
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new handlers and test fixes
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2025-04-16 20:54:08 +03:00 |
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f654f64c71
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Created dedicated Mul namespace for MUL instruction handlers. Implemented MulRm8Handler for MUL r/m8 instruction (opcode F6 /4) and moved MulRm32Handler to the new namespace. Updated InstructionHandlerFactory to register both handlers.
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2025-04-16 20:43:06 +03:00 |
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d2279f4720
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Added NegRm8Handler for NEG r/m8 instruction (opcode F6 /3). Registered the new handler in InstructionHandlerFactory.
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2025-04-16 20:29:26 +03:00 |
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